12a81f60b9
This patch make some cleanup in HW names Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
290 lines
13 KiB
C
290 lines
13 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* James P. Ketrenos <ipw2100-admin@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef __iwl_prph_h__
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#define __iwl_prph_h__
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/*
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* Registers in this file are internal, not PCI bus memory mapped.
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* Driver accesses these via HBUS_TARG_PRPH_* registers.
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*/
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#define PRPH_BASE (0x00000)
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#define PRPH_END (0xFFFFF)
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/* APMG (power management) constants */
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#define APMG_BASE (PRPH_BASE + 0x3000)
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#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
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#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
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#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
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#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
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#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
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#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
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#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
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#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
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#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
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#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
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#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000)
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/**
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* BSM (Bootstrap State Machine)
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*
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* The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
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* in special SRAM that does not power down when the embedded control
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* processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
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*
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* When powering back up after sleeps (or during initial uCode load), the BSM
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* internally loads the short bootstrap program from the special SRAM into the
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* embedded processor's instruction SRAM, and starts the processor so it runs
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* the bootstrap program.
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*
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* This bootstrap program loads (via PCI busmaster DMA) instructions and data
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* images for a uCode program from host DRAM locations. The host driver
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* indicates DRAM locations and sizes for instruction and data images via the
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* four BSM_DRAM_* registers. Once the bootstrap program loads the new program,
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* the new program starts automatically.
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*
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* The uCode used for open-source drivers includes two programs:
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*
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* 1) Initialization -- performs hardware calibration and sets up some
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* internal data, then notifies host via "initialize alive" notification
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* (struct iwl_init_alive_resp) that it has completed all of its work.
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* After signal from host, it then loads and starts the runtime program.
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* The initialization program must be used when initially setting up the
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* NIC after loading the driver.
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*
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* 2) Runtime/Protocol -- performs all normal runtime operations. This
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* notifies host via "alive" notification (struct iwl_alive_resp) that it
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* is ready to be used.
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*
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* When initializing the NIC, the host driver does the following procedure:
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*
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* 1) Load bootstrap program (instructions only, no data image for bootstrap)
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* into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND
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*
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* 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction
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* images in host DRAM.
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*
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* 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked:
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* BSM_WR_MEM_SRC_REG = 0
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* BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND
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* BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image
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*
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* 4) Load bootstrap into instruction SRAM:
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* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START
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*
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* 5) Wait for load completion:
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* Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0
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*
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* 6) Enable future boot loads whenever NIC's power management triggers it:
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* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN
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*
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* 7) Start the NIC by removing all reset bits:
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* CSR_RESET = 0
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*
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* The bootstrap uCode (already in instruction SRAM) loads initialization
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* uCode. Initialization uCode performs data initialization, sends
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* "initialize alive" notification to host, and waits for a signal from
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* host to load runtime code.
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*
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* 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction
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* images in host DRAM. The last register loaded must be the instruction
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* bytecount register ("1" in MSbit tells initialization uCode to load
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* the runtime uCode):
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* BSM_DRAM_INST_BYTECOUNT_REG = bytecount | BSM_DRAM_INST_LOAD
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*
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* 5) Wait for "alive" notification, then issue normal runtime commands.
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*
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* Data caching during power-downs:
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*
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* Just before the embedded controller powers down (e.g for automatic
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* power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
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* a current snapshot of the embedded processor's data SRAM into host DRAM.
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* This caches the data while the embedded processor's memory is powered down.
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* Location and size are controlled by BSM_DRAM_DATA_* registers.
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*
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* NOTE: Instruction SRAM does not need to be saved, since that doesn't
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* change during operation; the original image (from uCode distribution
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* file) can be used for reload.
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*
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* When powering back up, the BSM loads the bootstrap program. Bootstrap looks
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* at the BSM_DRAM_* registers, which now point to the runtime instruction
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* image and the cached (modified) runtime data (*not* the initialization
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* uCode). Bootstrap reloads these runtime images into SRAM, and restarts the
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* uCode from where it left off before the power-down.
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*
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* NOTE: Initialization uCode does *not* run as part of the save/restore
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* procedure.
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*
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* This save/restore method is mostly for autonomous power management during
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* normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and
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* RFKILL should use complete restarts (with total re-initialization) of uCode,
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* allowing total shutdown (including BSM memory).
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*
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* Note that, during normal operation, the host DRAM that held the initial
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* startup data for the runtime code is now being used as a backup data cache
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* for modified data! If you need to completely re-initialize the NIC, make
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* sure that you use the runtime data image from the uCode distribution file,
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* not the modified/saved runtime data. You may want to store a separate
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* "clean" runtime data image in DRAM to avoid disk reads of distribution file.
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*/
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/* BSM bit fields */
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#define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */
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#define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/
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#define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */
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/* BSM addresses */
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#define BSM_BASE (PRPH_BASE + 0x3400)
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#define BSM_END (PRPH_BASE + 0x3800)
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#define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
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#define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
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#define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
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#define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
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#define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
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/*
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* Pointers and size regs for bootstrap load and data SRAM save/restore.
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* NOTE: 3945 pointers use bits 31:0 of DRAM address.
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* 4965 pointers use bits 35:4 of DRAM address.
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*/
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#define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
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#define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
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#define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
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#define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
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/*
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* BSM special memory, stays powered on during power-save sleeps.
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* Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
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*/
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#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
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#define BSM_SRAM_SIZE (1024) /* bytes */
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/* 3945 Tx scheduler registers */
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#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
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#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
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#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
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#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
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#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
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#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
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#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
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#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
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/*
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* 4965 Tx Scheduler registers.
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* Details are documented in iwl-4965-hw.h
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*/
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#define IWL49_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_BASE + 0x0)
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#define IWL49_SCD_EMPTY_BITS (IWL49_SCD_BASE + 0x4)
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#define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_BASE + 0x10)
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#define IWL49_SCD_AIT (IWL49_SCD_BASE + 0x18)
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#define IWL49_SCD_TXFACT (IWL49_SCD_BASE + 0x1c)
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#define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_BASE + 0x24 + (x) * 4)
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#define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_BASE + 0x64 + (x) * 4)
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#define IWL49_SCD_SETQUEUENUM (IWL49_SCD_BASE + 0xa4)
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#define IWL49_SCD_SET_TXSTAT_TXED (IWL49_SCD_BASE + 0xa8)
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#define IWL49_SCD_SET_TXSTAT_DONE (IWL49_SCD_BASE + 0xac)
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#define IWL49_SCD_SET_TXSTAT_NOT_SCHD (IWL49_SCD_BASE + 0xb0)
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#define IWL49_SCD_DECREASE_CREDIT (IWL49_SCD_BASE + 0xb4)
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#define IWL49_SCD_DECREASE_SCREDIT (IWL49_SCD_BASE + 0xb8)
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#define IWL49_SCD_LOAD_CREDIT (IWL49_SCD_BASE + 0xbc)
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#define IWL49_SCD_LOAD_SCREDIT (IWL49_SCD_BASE + 0xc0)
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#define IWL49_SCD_BAR (IWL49_SCD_BASE + 0xc4)
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#define IWL49_SCD_BAR_DW0 (IWL49_SCD_BASE + 0xc8)
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#define IWL49_SCD_BAR_DW1 (IWL49_SCD_BASE + 0xcc)
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#define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_BASE + 0xd0)
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#define IWL49_SCD_QUERY_REQ (IWL49_SCD_BASE + 0xd8)
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#define IWL49_SCD_QUERY_RES (IWL49_SCD_BASE + 0xdc)
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#define IWL49_SCD_PENDING_FRAMES (IWL49_SCD_BASE + 0xe0)
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#define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_BASE + 0xe4)
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#define IWL49_SCD_INTERRUPT_THRESHOLD (IWL49_SCD_BASE + 0xe8)
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#define IWL49_SCD_QUERY_MIN_FRAME_SIZE (IWL49_SCD_BASE + 0x100)
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#define IWL49_SCD_QUEUE_STATUS_BITS(x) (IWL49_SCD_BASE + 0x104 + (x) * 4)
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/* SP SCD */
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#define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
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#define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8)
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#define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c)
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#define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10)
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#define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14)
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#define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4)
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#define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4)
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#define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8)
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#define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248)
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#define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108)
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#define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4)
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#endif /* __iwl_prph_h__ */
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