513 lines
15 KiB
C
513 lines
15 KiB
C
/* $Id: math.c,v 1.11 1999/12/20 05:02:25 davem Exp $
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* arch/sparc64/math-emu/math.c
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*
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* Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*
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* Emulation routines originate from soft-fp package, which is part
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* of glibc and has appropriate copyrights in it.
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*/
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <asm/fpumacro.h>
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#include <asm/ptrace.h>
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#include <asm/uaccess.h>
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#include "sfp-util.h"
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#include <math-emu/soft-fp.h>
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#include <math-emu/single.h>
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#include <math-emu/double.h>
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#include <math-emu/quad.h>
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/* QUAD - ftt == 3 */
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#define FMOVQ 0x003
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#define FNEGQ 0x007
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#define FABSQ 0x00b
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#define FSQRTQ 0x02b
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#define FADDQ 0x043
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#define FSUBQ 0x047
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#define FMULQ 0x04b
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#define FDIVQ 0x04f
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#define FDMULQ 0x06e
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#define FQTOX 0x083
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#define FXTOQ 0x08c
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#define FQTOS 0x0c7
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#define FQTOD 0x0cb
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#define FITOQ 0x0cc
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#define FSTOQ 0x0cd
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#define FDTOQ 0x0ce
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#define FQTOI 0x0d3
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/* SUBNORMAL - ftt == 2 */
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#define FSQRTS 0x029
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#define FSQRTD 0x02a
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#define FADDS 0x041
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#define FADDD 0x042
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#define FSUBS 0x045
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#define FSUBD 0x046
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#define FMULS 0x049
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#define FMULD 0x04a
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#define FDIVS 0x04d
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#define FDIVD 0x04e
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#define FSMULD 0x069
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#define FSTOX 0x081
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#define FDTOX 0x082
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#define FDTOS 0x0c6
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#define FSTOD 0x0c9
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#define FSTOI 0x0d1
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#define FDTOI 0x0d2
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#define FXTOS 0x084 /* Only Ultra-III generates this. */
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#define FXTOD 0x088 /* Only Ultra-III generates this. */
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#if 0 /* Optimized inline in sparc64/kernel/entry.S */
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#define FITOS 0x0c4 /* Only Ultra-III generates this. */
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#endif
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#define FITOD 0x0c8 /* Only Ultra-III generates this. */
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/* FPOP2 */
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#define FCMPQ 0x053
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#define FCMPEQ 0x057
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#define FMOVQ0 0x003
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#define FMOVQ1 0x043
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#define FMOVQ2 0x083
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#define FMOVQ3 0x0c3
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#define FMOVQI 0x103
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#define FMOVQX 0x183
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#define FMOVQZ 0x027
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#define FMOVQLE 0x047
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#define FMOVQLZ 0x067
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#define FMOVQNZ 0x0a7
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#define FMOVQGZ 0x0c7
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#define FMOVQGE 0x0e7
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#define FSR_TEM_SHIFT 23UL
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#define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
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#define FSR_AEXC_SHIFT 5UL
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#define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
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#define FSR_CEXC_SHIFT 0UL
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#define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
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/* All routines returning an exception to raise should detect
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* such exceptions _before_ rounding to be consistent with
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* the behavior of the hardware in the implemented cases
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* (and thus with the recommendations in the V9 architecture
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* manual).
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*
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* We return 0 if a SIGFPE should be sent, 1 otherwise.
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*/
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static inline int record_exception(struct pt_regs *regs, int eflag)
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{
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u64 fsr = current_thread_info()->xfsr[0];
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int would_trap;
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/* Determine if this exception would have generated a trap. */
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would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
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/* If trapping, we only want to signal one bit. */
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if(would_trap != 0) {
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eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
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if((eflag & (eflag - 1)) != 0) {
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if(eflag & FP_EX_INVALID)
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eflag = FP_EX_INVALID;
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else if(eflag & FP_EX_OVERFLOW)
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eflag = FP_EX_OVERFLOW;
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else if(eflag & FP_EX_UNDERFLOW)
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eflag = FP_EX_UNDERFLOW;
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else if(eflag & FP_EX_DIVZERO)
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eflag = FP_EX_DIVZERO;
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else if(eflag & FP_EX_INEXACT)
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eflag = FP_EX_INEXACT;
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}
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}
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/* Set CEXC, here is the rule:
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*
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* In general all FPU ops will set one and only one
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* bit in the CEXC field, this is always the case
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* when the IEEE exception trap is enabled in TEM.
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*/
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fsr &= ~(FSR_CEXC_MASK);
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fsr |= ((long)eflag << FSR_CEXC_SHIFT);
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/* Set the AEXC field, rule is:
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*
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* If a trap would not be generated, the
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* CEXC just generated is OR'd into the
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* existing value of AEXC.
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*/
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if(would_trap == 0)
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fsr |= ((long)eflag << FSR_AEXC_SHIFT);
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/* If trapping, indicate fault trap type IEEE. */
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if(would_trap != 0)
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fsr |= (1UL << 14);
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current_thread_info()->xfsr[0] = fsr;
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/* If we will not trap, advance the program counter over
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* the instruction being handled.
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*/
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if(would_trap == 0) {
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regs->tpc = regs->tnpc;
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regs->tnpc += 4;
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}
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return (would_trap ? 0 : 1);
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}
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typedef union {
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u32 s;
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u64 d;
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u64 q[2];
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} *argp;
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int do_mathemu(struct pt_regs *regs, struct fpustate *f)
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{
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unsigned long pc = regs->tpc;
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unsigned long tstate = regs->tstate;
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u32 insn = 0;
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int type = 0;
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/* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
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whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
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non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
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#define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
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int freg;
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static u64 zero[2] = { 0L, 0L };
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int flags;
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FP_DECL_EX;
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FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
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FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
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FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
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int IR;
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long XR, xfsr;
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if (tstate & TSTATE_PRIV)
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die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
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if (test_thread_flag(TIF_32BIT))
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pc = (u32)pc;
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if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
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if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
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switch ((insn >> 5) & 0x1ff) {
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/* QUAD - ftt == 3 */
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case FMOVQ:
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case FNEGQ:
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case FABSQ: TYPE(3,3,0,3,0,0,0); break;
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case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
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case FADDQ:
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case FSUBQ:
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case FMULQ:
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case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
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case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
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case FQTOX: TYPE(3,2,0,3,1,0,0); break;
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case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
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case FQTOS: TYPE(3,1,1,3,1,0,0); break;
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case FQTOD: TYPE(3,2,1,3,1,0,0); break;
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case FITOQ: TYPE(3,3,1,1,0,0,0); break;
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case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
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case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
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case FQTOI: TYPE(3,1,0,3,1,0,0); break;
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/* We can get either unimplemented or unfinished
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* for these cases. Pre-Niagara systems generate
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* unfinished fpop for SUBNORMAL cases, and Niagara
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* always gives unimplemented fpop for fsqrt{s,d}.
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*/
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case FSQRTS: {
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unsigned long x = current_thread_info()->xfsr[0];
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x = (x >> 14) & 0xf;
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TYPE(x,1,1,1,1,0,0);
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break;
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}
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case FSQRTD: {
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unsigned long x = current_thread_info()->xfsr[0];
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x = (x >> 14) & 0xf;
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TYPE(x,2,1,2,1,0,0);
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break;
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}
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/* SUBNORMAL - ftt == 2 */
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case FADDD:
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case FSUBD:
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case FMULD:
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case FDIVD: TYPE(2,2,1,2,1,2,1); break;
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case FADDS:
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case FSUBS:
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case FMULS:
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case FDIVS: TYPE(2,1,1,1,1,1,1); break;
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case FSMULD: TYPE(2,2,1,1,1,1,1); break;
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case FSTOX: TYPE(2,2,0,1,1,0,0); break;
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case FDTOX: TYPE(2,2,0,2,1,0,0); break;
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case FDTOS: TYPE(2,1,1,2,1,0,0); break;
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case FSTOD: TYPE(2,2,1,1,1,0,0); break;
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case FSTOI: TYPE(2,1,0,1,1,0,0); break;
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case FDTOI: TYPE(2,1,0,2,1,0,0); break;
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/* Only Ultra-III generates these */
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case FXTOS: TYPE(2,1,1,2,0,0,0); break;
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case FXTOD: TYPE(2,2,1,2,0,0,0); break;
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#if 0 /* Optimized inline in sparc64/kernel/entry.S */
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case FITOS: TYPE(2,1,1,1,0,0,0); break;
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#endif
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case FITOD: TYPE(2,2,1,1,0,0,0); break;
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}
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}
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else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
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IR = 2;
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switch ((insn >> 5) & 0x1ff) {
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case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
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case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
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/* Now the conditional fmovq support */
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case FMOVQ0:
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case FMOVQ1:
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case FMOVQ2:
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case FMOVQ3:
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/* fmovq %fccX, %fY, %fZ */
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if (!((insn >> 11) & 3))
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XR = current_thread_info()->xfsr[0] >> 10;
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else
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XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
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XR &= 3;
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IR = 0;
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switch ((insn >> 14) & 0x7) {
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/* case 0: IR = 0; break; */ /* Never */
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case 1: if (XR) IR = 1; break; /* Not Equal */
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case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
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case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
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case 4: if (XR == 1) IR = 1; break; /* Less */
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case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
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case 6: if (XR == 2) IR = 1; break; /* Greater */
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case 7: if (XR == 3) IR = 1; break; /* Unordered */
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}
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if ((insn >> 14) & 8)
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IR ^= 1;
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break;
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case FMOVQI:
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case FMOVQX:
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/* fmovq %[ix]cc, %fY, %fZ */
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XR = regs->tstate >> 32;
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if ((insn >> 5) & 0x80)
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XR >>= 4;
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XR &= 0xf;
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IR = 0;
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freg = ((XR >> 2) ^ XR) & 2;
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switch ((insn >> 14) & 0x7) {
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/* case 0: IR = 0; break; */ /* Never */
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case 1: if (XR & 4) IR = 1; break; /* Equal */
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case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
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case 3: if (freg) IR = 1; break; /* Less */
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case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
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case 5: if (XR & 1) IR = 1; break; /* Carry Set */
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case 6: if (XR & 8) IR = 1; break; /* Negative */
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case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
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}
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if ((insn >> 14) & 8)
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IR ^= 1;
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break;
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case FMOVQZ:
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case FMOVQLE:
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case FMOVQLZ:
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case FMOVQNZ:
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case FMOVQGZ:
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case FMOVQGE:
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freg = (insn >> 14) & 0x1f;
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if (!freg)
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XR = 0;
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else if (freg < 16)
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XR = regs->u_regs[freg];
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else if (test_thread_flag(TIF_32BIT)) {
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struct reg_window32 __user *win32;
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flushw_user ();
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
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get_user(XR, &win32->locals[freg - 16]);
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} else {
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struct reg_window __user *win;
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flushw_user ();
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win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
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get_user(XR, &win->locals[freg - 16]);
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}
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IR = 0;
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switch ((insn >> 10) & 3) {
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case 1: if (!XR) IR = 1; break; /* Register Zero */
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case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
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case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
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}
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if ((insn >> 10) & 4)
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IR ^= 1;
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break;
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}
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if (IR == 0) {
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/* The fmov test was false. Do a nop instead */
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current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
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regs->tpc = regs->tnpc;
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regs->tnpc += 4;
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return 1;
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} else if (IR == 1) {
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/* Change the instruction into plain fmovq */
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insn = (insn & 0x3e00001f) | 0x81a00060;
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TYPE(3,3,0,3,0,0,0);
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}
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}
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}
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if (type) {
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argp rs1 = NULL, rs2 = NULL, rd = NULL;
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freg = (current_thread_info()->xfsr[0] >> 14) & 0xf;
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if (freg != (type >> 9))
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goto err;
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current_thread_info()->xfsr[0] &= ~0x1c000;
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freg = ((insn >> 14) & 0x1f);
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switch (type & 0x3) {
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case 3: if (freg & 2) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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goto err;
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}
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case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
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case 1: rs1 = (argp)&f->regs[freg];
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flags = (freg < 32) ? FPRS_DL : FPRS_DU;
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if (!(current_thread_info()->fpsaved[0] & flags))
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rs1 = (argp)&zero;
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break;
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}
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switch (type & 0x7) {
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case 7: FP_UNPACK_QP (QA, rs1); break;
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case 6: FP_UNPACK_DP (DA, rs1); break;
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case 5: FP_UNPACK_SP (SA, rs1); break;
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}
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freg = (insn & 0x1f);
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switch ((type >> 3) & 0x3) {
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case 3: if (freg & 2) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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goto err;
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}
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case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
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case 1: rs2 = (argp)&f->regs[freg];
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flags = (freg < 32) ? FPRS_DL : FPRS_DU;
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if (!(current_thread_info()->fpsaved[0] & flags))
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rs2 = (argp)&zero;
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break;
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}
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switch ((type >> 3) & 0x7) {
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case 7: FP_UNPACK_QP (QB, rs2); break;
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case 6: FP_UNPACK_DP (DB, rs2); break;
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case 5: FP_UNPACK_SP (SB, rs2); break;
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}
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freg = ((insn >> 25) & 0x1f);
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switch ((type >> 6) & 0x3) {
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case 3: if (freg & 2) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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goto err;
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}
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case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
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case 1: rd = (argp)&f->regs[freg];
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flags = (freg < 32) ? FPRS_DL : FPRS_DU;
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if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
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current_thread_info()->fpsaved[0] = FPRS_FEF;
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current_thread_info()->gsr[0] = 0;
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}
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if (!(current_thread_info()->fpsaved[0] & flags)) {
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if (freg < 32)
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memset(f->regs, 0, 32*sizeof(u32));
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else
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memset(f->regs+32, 0, 32*sizeof(u32));
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}
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current_thread_info()->fpsaved[0] |= flags;
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break;
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}
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switch ((insn >> 5) & 0x1ff) {
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/* + */
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case FADDS: FP_ADD_S (SR, SA, SB); break;
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case FADDD: FP_ADD_D (DR, DA, DB); break;
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case FADDQ: FP_ADD_Q (QR, QA, QB); break;
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/* - */
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case FSUBS: FP_SUB_S (SR, SA, SB); break;
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case FSUBD: FP_SUB_D (DR, DA, DB); break;
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case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
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/* * */
|
|
case FMULS: FP_MUL_S (SR, SA, SB); break;
|
|
case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
|
|
FP_CONV (D, S, 1, 1, DB, SB);
|
|
case FMULD: FP_MUL_D (DR, DA, DB); break;
|
|
case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
|
|
FP_CONV (Q, D, 2, 1, QB, DB);
|
|
case FMULQ: FP_MUL_Q (QR, QA, QB); break;
|
|
/* / */
|
|
case FDIVS: FP_DIV_S (SR, SA, SB); break;
|
|
case FDIVD: FP_DIV_D (DR, DA, DB); break;
|
|
case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
|
|
/* sqrt */
|
|
case FSQRTS: FP_SQRT_S (SR, SB); break;
|
|
case FSQRTD: FP_SQRT_D (DR, DB); break;
|
|
case FSQRTQ: FP_SQRT_Q (QR, QB); break;
|
|
/* mov */
|
|
case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
|
|
case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
|
|
case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
|
|
/* float to int */
|
|
case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
|
|
case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
|
|
case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
|
|
case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
|
|
case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
|
|
case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
|
|
/* int to float */
|
|
case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
|
|
case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
|
|
/* Only Ultra-III generates these */
|
|
case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
|
|
case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
|
|
#if 0 /* Optimized inline in sparc64/kernel/entry.S */
|
|
case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
|
|
#endif
|
|
case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
|
|
/* float to float */
|
|
case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
|
|
case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
|
|
case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
|
|
case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
|
|
case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
|
|
case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
|
|
/* comparison */
|
|
case FCMPQ:
|
|
case FCMPEQ:
|
|
FP_CMP_Q(XR, QB, QA, 3);
|
|
if (XR == 3 &&
|
|
(((insn >> 5) & 0x1ff) == FCMPEQ ||
|
|
FP_ISSIGNAN_Q(QA) ||
|
|
FP_ISSIGNAN_Q(QB)))
|
|
FP_SET_EXCEPTION (FP_EX_INVALID);
|
|
}
|
|
if (!FP_INHIBIT_RESULTS) {
|
|
switch ((type >> 6) & 0x7) {
|
|
case 0: xfsr = current_thread_info()->xfsr[0];
|
|
if (XR == -1) XR = 2;
|
|
switch (freg & 3) {
|
|
/* fcc0, 1, 2, 3 */
|
|
case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
|
|
case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
|
|
case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
|
|
case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
|
|
}
|
|
current_thread_info()->xfsr[0] = xfsr;
|
|
break;
|
|
case 1: rd->s = IR; break;
|
|
case 2: rd->d = XR; break;
|
|
case 5: FP_PACK_SP (rd, SR); break;
|
|
case 6: FP_PACK_DP (rd, DR); break;
|
|
case 7: FP_PACK_QP (rd, QR); break;
|
|
}
|
|
}
|
|
|
|
if(_fex != 0)
|
|
return record_exception(regs, _fex);
|
|
|
|
/* Success and no exceptions detected. */
|
|
current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
|
|
regs->tpc = regs->tnpc;
|
|
regs->tnpc += 4;
|
|
return 1;
|
|
}
|
|
err: return 0;
|
|
}
|