f16295e7e7
Fix CCLK and SCLK checks, combine all arch checks into one file for maintance. Checkins that remove more lines than they add are always good. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
184 lines
5.1 KiB
C
184 lines
5.1 KiB
C
/*
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* File: include/asm-blackfin/mach-bf548/bf548.h
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* Based on:
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* Author:
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*
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* Created:
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* Description: System MMR register and memory map for ADSP-BF548
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MACH_BF548_H__
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#define __MACH_BF548_H__
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#define SUPPORTED_REVID 0
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#define OFFSET_(x) ((x) & 0x0000FFFF)
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/*some misc defines*/
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#define IMASK_IVG15 0x8000
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#define IMASK_IVG14 0x4000
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#define IMASK_IVG13 0x2000
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#define IMASK_IVG12 0x1000
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#define IMASK_IVG11 0x0800
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#define IMASK_IVG10 0x0400
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#define IMASK_IVG9 0x0200
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#define IMASK_IVG8 0x0100
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#define IMASK_IVG7 0x0080
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#define IMASK_IVGTMR 0x0040
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#define IMASK_IVGHW 0x0020
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/***************************/
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#define BLKFIN_DSUBBANKS 4
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#define BLKFIN_DWAYS 2
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#define BLKFIN_DLINES 64
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#define BLKFIN_ISUBBANKS 4
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#define BLKFIN_IWAYS 4
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#define BLKFIN_ILINES 32
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#define WAY0_L 0x1
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#define WAY1_L 0x2
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#define WAY01_L 0x3
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#define WAY2_L 0x4
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#define WAY02_L 0x5
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#define WAY12_L 0x6
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#define WAY012_L 0x7
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#define WAY3_L 0x8
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#define WAY03_L 0x9
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#define WAY13_L 0xA
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#define WAY013_L 0xB
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#define WAY32_L 0xC
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#define WAY320_L 0xD
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#define WAY321_L 0xE
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#define WAYALL_L 0xF
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#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
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/********************************* EBIU Settings ************************************/
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#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
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#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
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#ifdef CONFIG_C_AMBEN_ALL
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#define V_AMBEN AMBEN_ALL
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#endif
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#ifdef CONFIG_C_AMBEN
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#define V_AMBEN 0x0
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#endif
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#ifdef CONFIG_C_AMBEN_B0
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#define V_AMBEN AMBEN_B0
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#endif
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#ifdef CONFIG_C_AMBEN_B0_B1
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#define V_AMBEN AMBEN_B0_B1
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#endif
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#ifdef CONFIG_C_AMBEN_B0_B1_B2
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#define V_AMBEN AMBEN_B0_B1_B2
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#endif
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#ifdef CONFIG_C_AMCKEN
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#define V_AMCKEN AMCKEN
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#else
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#define V_AMCKEN 0x0
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#endif
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
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#ifdef CONFIG_BF542
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#define CPU "BF542"
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#define CPUID 0x027c8000
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#endif
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#ifdef CONFIG_BF544
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#define CPU "BF544"
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#define CPUID 0x027c8000
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#endif
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#ifdef CONFIG_BF548
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#define CPU "BF548"
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#define CPUID 0x027c6000
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#endif
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#ifdef CONFIG_BF549
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#define CPU "BF549"
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#endif
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#ifndef CPU
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#define CPU "UNKNOWN"
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#define CPUID 0x0
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#endif
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#if (CONFIG_MEM_SIZE % 4)
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#error "SDRAM mem size must be multible of 4MB"
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#endif
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
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#define ANOMALY_05000158_WORKAROUND 0x200
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#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
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| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#else /*Write Through */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
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| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#endif
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#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
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#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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#define MAX_CPLBS (16 * 2)
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
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#endif /* __MACH_BF48_H__ */
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