f7eee89b2a
Add support for the Atmel AT91SAM9XE range of processors. These are basically AT91SAM9260's with different amounts of internal SRAM and Flash. We make use of the existing AT91SAM9260 support, but just perform run-time detection of the size of the internal SRAM. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
367 lines
8.6 KiB
C
367 lines
8.6 KiB
C
/*
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* arch/arm/mach-at91/at91sam9260.c
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*
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* Copyright (C) 2006 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9260_io_desc[] __initdata = {
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{
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.virtual = AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}
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};
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static struct map_desc at91sam9260_sram_desc[] __initdata = {
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{
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
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.length = AT91SAM9260_SRAM0_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
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.length = AT91SAM9260_SRAM1_SIZE,
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.type = MT_DEVICE,
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}
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};
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static struct map_desc at91sam9xe_sram_desc[] __initdata = {
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{
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.pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
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.type = MT_DEVICE,
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}
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "macb_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart4_clk = {
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.name = "usart4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart5_clk = {
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.name = "usart5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc3_clk = {
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.name = "tc3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc4_clk = {
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.name = "tc4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc5_clk = {
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.name = "tc5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&adc_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc_clk,
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&udc_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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// ssc
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&ohci_clk,
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&macb_clk,
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&isi_clk,
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&usart3_clk,
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&usart4_clk,
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&usart5_clk,
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&tc3_clk,
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&tc4_clk,
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&tc5_clk,
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// irq0 .. irq2
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9260_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9260_gpio[] = {
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{
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.id = AT91SAM9260_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9260_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9260_ID_PIOC,
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.offset = AT91_PIOC,
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.clock = &pioC_clk,
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}
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};
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static void at91sam9260_reset(void)
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{
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at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9260 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9xe_initialize(void)
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{
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unsigned long cidr, sram_size;
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cidr = at91_sys_read(AT91_DBGU_CIDR);
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switch (cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
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at91sam9xe_sram_desc->length = sram_size;
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iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
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}
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void __init at91sam9260_initialize(unsigned long main_clock)
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{
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/* Map peripherals */
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iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
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if (cpu_is_at91sam9xe())
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at91sam9xe_initialize();
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else
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iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
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at91_arch_reset = at91sam9260_reset;
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at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9260_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9260_gpio, 3);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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0, /* Parallel IO Controller A */
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0, /* Parallel IO Controller B */
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0, /* Parallel IO Controller C */
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0, /* Analog-to-Digital Converter */
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6, /* USART 0 */
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6, /* USART 1 */
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6, /* USART 2 */
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0, /* Multimedia Card Interface */
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4, /* USB Device Port */
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0, /* Two-Wire Interface */
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6, /* Serial Peripheral Interface 0 */
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6, /* Serial Peripheral Interface 1 */
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5, /* Serial Synchronous Controller */
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0,
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0,
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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3, /* USB Host port */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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6, /* USART 3 */
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6, /* USART 4 */
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6, /* USART 5 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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};
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void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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if (!priority)
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priority = at91sam9260_default_irq_priority;
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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