251b928cdf
Patch from Kenneth Tan The get_irqnr_and_base subroutine of ixp4xx does not take interrupt 0 condition into account properly. We should not perform "subs" here. The Z flag will be set when interrupt 0 occur, which resulting "movne r1, sp" in the caller routine (irq_handler) not being executed. When interrupt 0 occur: o if CONFIG_CPU_IXP46X is not set, "subs" will set the Z flag and return o if CONFIG_CPU_IXP46X is set, codes in upper interrupt handling will be trigerred. But since this is not supper interrupt, the "cmp" in the upper interrupt handling portion will set the Z flag and return Signed-off-by: Kenneth Tan <chong.yin.tan@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
40 lines
996 B
ArmAsm
40 lines
996 B
ArmAsm
/*
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* include/asm-arm/arch-ixp4xx/entry-macro.S
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*
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* Low-level IRQ helper macros for IXP4xx-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
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ldr \irqstat, [\irqstat] @ get interrupts
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cmp \irqstat, #0
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beq 1001f @ upper IRQ?
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clz \irqnr, \irqstat
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mov \base, #31
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sub \irqnr, \base, \irqnr
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b 1002f @ lower IRQ being
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@ handled
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1001:
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/*
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* IXP465 has an upper IRQ status register
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*/
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#if defined(CONFIG_CPU_IXP46X)
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
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ldr \irqstat, [\irqstat] @ get upper interrupts
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mov \irqnr, #63
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clz \irqstat, \irqstat
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cmp \irqstat, #32
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subne \irqnr, \irqnr, \irqstat
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#endif
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1002:
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.endm
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