feb4722552
Modify the common at91 hardware support to deal with the non-MMU at91x40 family. The base RAM (which is most likely not DRAM) is set to the configured value. Virtual IO device mapping is set to be 1 to 1 with the physical addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/*
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* include/asm-arm/arch-at91/hardware.h
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2003 ATMEL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/sizes.h>
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#if defined(CONFIG_ARCH_AT91RM9200)
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#include <asm/arch/at91rm9200.h>
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#elif defined(CONFIG_ARCH_AT91SAM9260)
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#include <asm/arch/at91sam9260.h>
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#elif defined(CONFIG_ARCH_AT91SAM9261)
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#include <asm/arch/at91sam9261.h>
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#elif defined(CONFIG_ARCH_AT91SAM9263)
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#include <asm/arch/at91sam9263.h>
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#elif defined(CONFIG_ARCH_AT91SAM9RL)
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#include <asm/arch/at91sam9rl.h>
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#elif defined(CONFIG_ARCH_AT91X40)
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#include <asm/arch/at91x40.h>
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#else
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#error "Unsupported AT91 processor"
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#endif
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#ifdef CONFIG_MMU
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/*
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* Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
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* to 0xFEF78000 .. 0xFF000000. (544Kb)
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*/
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#define AT91_IO_PHYS_BASE 0xFFF78000
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#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
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#else
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/*
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* Identity mapping for the non MMU case.
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*/
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#define AT91_IO_PHYS_BASE AT91_BASE_SYS
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#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE
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#endif
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#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
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/* Convert a physical IO address to virtual IO address */
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#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
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/*
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* Virtual to Physical Address mapping for IO devices.
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*/
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#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
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#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
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/* Internal SRAM is mapped below the IO devices */
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#define AT91_SRAM_MAX SZ_1M
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#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
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/* Serial ports */
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#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
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/* External Memory Map */
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#define AT91_CHIPSELECT_0 0x10000000
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#define AT91_CHIPSELECT_1 0x20000000
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#define AT91_CHIPSELECT_2 0x30000000
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#define AT91_CHIPSELECT_3 0x40000000
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#define AT91_CHIPSELECT_4 0x50000000
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#define AT91_CHIPSELECT_5 0x60000000
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#define AT91_CHIPSELECT_6 0x70000000
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#define AT91_CHIPSELECT_7 0x80000000
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/* SDRAM */
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#ifdef CONFIG_DRAM_BASE
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#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
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#else
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#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
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#endif
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/* Clocks */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#endif
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