584 lines
13 KiB
C
584 lines
13 KiB
C
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/*
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* Critical Link MityOMAP-L138 SoM
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*
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* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of
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* any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/partitions.h>
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#include <linux/regulator/machine.h>
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#include <linux/i2c.h>
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#include <linux/platform_data/at24.h>
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#include <linux/etherdevice.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/common.h>
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#include <mach/cp_intc.h>
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#include <mach/da8xx.h>
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#include <linux/platform_data/mtd-davinci.h>
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#include <linux/platform_data/mtd-davinci-aemif.h>
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#include <mach/mux.h>
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#include <linux/platform_data/spi-davinci.h>
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#define MITYOMAPL138_PHY_ID ""
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#define FACTORY_CONFIG_MAGIC 0x012C0138
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#define FACTORY_CONFIG_VERSION 0x00010001
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/* Data Held in On-Board I2C device */
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struct factory_config {
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u32 magic;
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u32 version;
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u8 mac[6];
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u32 fpga_type;
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u32 spare;
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u32 serialnumber;
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char partnum[32];
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};
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static struct factory_config factory_config;
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struct part_no_info {
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const char *part_no; /* part number string of interest */
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int max_freq; /* khz */
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};
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static struct part_no_info mityomapl138_pn_info[] = {
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{
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.part_no = "L138-C",
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.max_freq = 300000,
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},
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{
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.part_no = "L138-D",
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.max_freq = 375000,
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},
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{
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.part_no = "L138-F",
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.max_freq = 456000,
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},
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{
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.part_no = "1808-C",
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.max_freq = 300000,
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},
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{
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.part_no = "1808-D",
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.max_freq = 375000,
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},
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{
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.part_no = "1808-F",
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.max_freq = 456000,
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},
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{
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.part_no = "1810-D",
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.max_freq = 375000,
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},
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};
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#ifdef CONFIG_CPU_FREQ
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static void mityomapl138_cpufreq_init(const char *partnum)
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{
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int i, ret;
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for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
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/*
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* the part number has additional characters beyond what is
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* stored in the table. This information is not needed for
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* determining the speed grade, and would require several
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* more table entries. Only check the first N characters
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* for a match.
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*/
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if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
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strlen(mityomapl138_pn_info[i].part_no))) {
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da850_max_speed = mityomapl138_pn_info[i].max_freq;
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break;
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}
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}
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ret = da850_register_cpufreq("pll0_sysclk3");
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if (ret)
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pr_warning("cpufreq registration failed: %d\n", ret);
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}
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#else
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static void mityomapl138_cpufreq_init(const char *partnum) { }
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#endif
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static void read_factory_config(struct memory_accessor *a, void *context)
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{
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int ret;
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const char *partnum = NULL;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
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if (ret != sizeof(struct factory_config)) {
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pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
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ret);
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goto bad_config;
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}
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if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
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pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
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factory_config.magic);
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goto bad_config;
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}
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if (factory_config.version != FACTORY_CONFIG_VERSION) {
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pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
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factory_config.version);
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goto bad_config;
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}
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pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
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if (is_valid_ether_addr(factory_config.mac))
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memcpy(soc_info->emac_pdata->mac_addr,
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factory_config.mac, ETH_ALEN);
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else
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pr_warning("MityOMAPL138: Invalid MAC found "
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"in factory config block\n");
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partnum = factory_config.partnum;
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pr_info("MityOMAPL138: Part Number = %s\n", partnum);
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bad_config:
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/* default maximum speed is valid for all platforms */
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mityomapl138_cpufreq_init(partnum);
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}
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static struct at24_platform_data mityomapl138_fd_chip = {
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.byte_len = 256,
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.page_size = 8,
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.flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
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.setup = read_factory_config,
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.context = NULL,
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};
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static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
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.bus_freq = 100, /* kHz */
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.bus_delay = 0, /* usec */
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};
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/* TPS65023 voltage regulator support */
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/* 1.2V Core */
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static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
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{
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.supply = "cvdd",
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},
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};
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/* 1.8V */
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static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
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{
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.supply = "usb0_vdda18",
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},
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{
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.supply = "usb1_vdda18",
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},
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{
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.supply = "ddr_dvdd18",
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},
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{
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.supply = "sata_vddr",
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},
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};
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/* 1.2V */
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static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
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{
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.supply = "sata_vdd",
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},
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{
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.supply = "usb_cvdd",
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},
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{
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.supply = "pll0_vdda",
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},
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{
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.supply = "pll1_vdda",
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},
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};
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/* 1.8V Aux LDO, not used */
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static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
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{
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.supply = "1.8v_aux",
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},
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};
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/* FPGA VCC Aux (2.5 or 3.3) LDO */
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static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
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{
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.supply = "vccaux",
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},
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};
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static struct regulator_init_data tps65023_regulator_data[] = {
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/* dcdc1 */
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{
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.constraints = {
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.min_uV = 1150000,
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.max_uV = 1350000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
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REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
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.consumer_supplies = tps65023_dcdc1_consumers,
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},
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/* dcdc2 */
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{
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.constraints = {
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.min_uV = 1800000,
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.max_uV = 1800000,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
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.consumer_supplies = tps65023_dcdc2_consumers,
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},
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/* dcdc3 */
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{
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.constraints = {
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.min_uV = 1200000,
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.max_uV = 1200000,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
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.consumer_supplies = tps65023_dcdc3_consumers,
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},
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/* ldo1 */
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{
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.constraints = {
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.min_uV = 1800000,
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.max_uV = 1800000,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
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.consumer_supplies = tps65023_ldo1_consumers,
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},
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/* ldo2 */
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{
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.constraints = {
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.min_uV = 2500000,
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.max_uV = 3300000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
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REGULATOR_CHANGE_STATUS,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
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.consumer_supplies = tps65023_ldo2_consumers,
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},
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};
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static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
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{
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I2C_BOARD_INFO("tps65023", 0x48),
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.platform_data = &tps65023_regulator_data[0],
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},
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{
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I2C_BOARD_INFO("24c02", 0x50),
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.platform_data = &mityomapl138_fd_chip,
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},
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};
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static int __init pmic_tps65023_init(void)
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{
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return i2c_register_board_info(1, mityomap_tps65023_info,
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ARRAY_SIZE(mityomap_tps65023_info));
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}
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/*
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* SPI Devices:
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* SPI1_CS0: 8M Flash ST-M25P64-VME6G
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||
|
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*/
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static struct mtd_partition spi_flash_partitions[] = {
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[0] = {
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.name = "ubl",
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.offset = 0,
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.size = SZ_64K,
|
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|
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.mask_flags = MTD_WRITEABLE,
|
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},
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[1] = {
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.name = "u-boot",
|
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|
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.offset = MTDPART_OFS_APPEND,
|
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.size = SZ_512K,
|
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|
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.mask_flags = MTD_WRITEABLE,
|
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|
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},
|
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[2] = {
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|
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.name = "u-boot-env",
|
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|
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.offset = MTDPART_OFS_APPEND,
|
||
|
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.size = SZ_64K,
|
||
|
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.mask_flags = MTD_WRITEABLE,
|
||
|
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},
|
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|
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[3] = {
|
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|
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.name = "periph-config",
|
||
|
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.offset = MTDPART_OFS_APPEND,
|
||
|
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.size = SZ_64K,
|
||
|
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.mask_flags = MTD_WRITEABLE,
|
||
|
|
},
|
||
|
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[4] = {
|
||
|
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.name = "reserved",
|
||
|
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.offset = MTDPART_OFS_APPEND,
|
||
|
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.size = SZ_256K + SZ_64K,
|
||
|
|
},
|
||
|
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[5] = {
|
||
|
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.name = "kernel",
|
||
|
|
.offset = MTDPART_OFS_APPEND,
|
||
|
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.size = SZ_2M + SZ_1M,
|
||
|
|
},
|
||
|
|
[6] = {
|
||
|
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.name = "fpga",
|
||
|
|
.offset = MTDPART_OFS_APPEND,
|
||
|
|
.size = SZ_2M,
|
||
|
|
},
|
||
|
|
[7] = {
|
||
|
|
.name = "spare",
|
||
|
|
.offset = MTDPART_OFS_APPEND,
|
||
|
|
.size = MTDPART_SIZ_FULL,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct flash_platform_data mityomapl138_spi_flash_data = {
|
||
|
|
.name = "m25p80",
|
||
|
|
.parts = spi_flash_partitions,
|
||
|
|
.nr_parts = ARRAY_SIZE(spi_flash_partitions),
|
||
|
|
.type = "m24p64",
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct davinci_spi_config spi_eprom_config = {
|
||
|
|
.io_type = SPI_IO_TYPE_DMA,
|
||
|
|
.c2tdelay = 8,
|
||
|
|
.t2cdelay = 8,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct spi_board_info mityomapl138_spi_flash_info[] = {
|
||
|
|
{
|
||
|
|
.modalias = "m25p80",
|
||
|
|
.platform_data = &mityomapl138_spi_flash_data,
|
||
|
|
.controller_data = &spi_eprom_config,
|
||
|
|
.mode = SPI_MODE_0,
|
||
|
|
.max_speed_hz = 30000000,
|
||
|
|
.bus_num = 1,
|
||
|
|
.chip_select = 0,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MityDSP-L138 includes a 256 MByte large-page NAND flash
|
||
|
|
* (128K blocks).
|
||
|
|
*/
|
||
|
|
static struct mtd_partition mityomapl138_nandflash_partition[] = {
|
||
|
|
{
|
||
|
|
.name = "rootfs",
|
||
|
|
.offset = 0,
|
||
|
|
.size = SZ_128M,
|
||
|
|
.mask_flags = 0, /* MTD_WRITEABLE, */
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.name = "homefs",
|
||
|
|
.offset = MTDPART_OFS_APPEND,
|
||
|
|
.size = MTDPART_SIZ_FULL,
|
||
|
|
.mask_flags = 0,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct davinci_nand_pdata mityomapl138_nandflash_data = {
|
||
|
|
.parts = mityomapl138_nandflash_partition,
|
||
|
|
.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
|
||
|
|
.ecc_mode = NAND_ECC_HW,
|
||
|
|
.bbt_options = NAND_BBT_USE_FLASH,
|
||
|
|
.options = NAND_BUSWIDTH_16,
|
||
|
|
.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource mityomapl138_nandflash_resource[] = {
|
||
|
|
{
|
||
|
|
.start = DA8XX_AEMIF_CS3_BASE,
|
||
|
|
.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.start = DA8XX_AEMIF_CTL_BASE,
|
||
|
|
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device mityomapl138_nandflash_device = {
|
||
|
|
.name = "davinci_nand",
|
||
|
|
.id = 1,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &mityomapl138_nandflash_data,
|
||
|
|
},
|
||
|
|
.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
|
||
|
|
.resource = mityomapl138_nandflash_resource,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device *mityomapl138_devices[] __initdata = {
|
||
|
|
&mityomapl138_nandflash_device,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void __init mityomapl138_setup_nand(void)
|
||
|
|
{
|
||
|
|
platform_add_devices(mityomapl138_devices,
|
||
|
|
ARRAY_SIZE(mityomapl138_devices));
|
||
|
|
|
||
|
|
if (davinci_aemif_setup(&mityomapl138_nandflash_device))
|
||
|
|
pr_warn("%s: Cannot configure AEMIF.\n", __func__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const short mityomap_mii_pins[] = {
|
||
|
|
DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
|
||
|
|
DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
|
||
|
|
DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
|
||
|
|
DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
|
||
|
|
DA850_MDIO_D,
|
||
|
|
-1
|
||
|
|
};
|
||
|
|
|
||
|
|
static const short mityomap_rmii_pins[] = {
|
||
|
|
DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
|
||
|
|
DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
|
||
|
|
DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
|
||
|
|
DA850_MDIO_D,
|
||
|
|
-1
|
||
|
|
};
|
||
|
|
|
||
|
|
static void __init mityomapl138_config_emac(void)
|
||
|
|
{
|
||
|
|
void __iomem *cfg_chip3_base;
|
||
|
|
int ret;
|
||
|
|
u32 val;
|
||
|
|
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||
|
|
|
||
|
|
soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
|
||
|
|
|
||
|
|
cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
|
||
|
|
val = __raw_readl(cfg_chip3_base);
|
||
|
|
|
||
|
|
if (soc_info->emac_pdata->rmii_en) {
|
||
|
|
val |= BIT(8);
|
||
|
|
ret = davinci_cfg_reg_list(mityomap_rmii_pins);
|
||
|
|
pr_info("RMII PHY configured\n");
|
||
|
|
} else {
|
||
|
|
val &= ~BIT(8);
|
||
|
|
ret = davinci_cfg_reg_list(mityomap_mii_pins);
|
||
|
|
pr_info("MII PHY configured\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
pr_warning("mii/rmii mux setup failed: %d\n", ret);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* configure the CFGCHIP3 register for RMII or MII */
|
||
|
|
__raw_writel(val, cfg_chip3_base);
|
||
|
|
|
||
|
|
soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
|
||
|
|
|
||
|
|
ret = da8xx_register_emac();
|
||
|
|
if (ret)
|
||
|
|
pr_warning("emac registration failed: %d\n", ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct davinci_pm_config da850_pm_pdata = {
|
||
|
|
.sleepcount = 128,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device da850_pm_device = {
|
||
|
|
.name = "pm-davinci",
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &da850_pm_pdata,
|
||
|
|
},
|
||
|
|
.id = -1,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void __init mityomapl138_init(void)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
/* for now, no special EDMA channels are reserved */
|
||
|
|
ret = da850_register_edma(NULL);
|
||
|
|
if (ret)
|
||
|
|
pr_warning("edma registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
ret = da8xx_register_watchdog();
|
||
|
|
if (ret)
|
||
|
|
pr_warning("watchdog registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
davinci_serial_init(da8xx_serial_device);
|
||
|
|
|
||
|
|
ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
|
||
|
|
if (ret)
|
||
|
|
pr_warning("i2c0 registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
ret = pmic_tps65023_init();
|
||
|
|
if (ret)
|
||
|
|
pr_warning("TPS65023 PMIC init failed: %d\n", ret);
|
||
|
|
|
||
|
|
mityomapl138_setup_nand();
|
||
|
|
|
||
|
|
ret = spi_register_board_info(mityomapl138_spi_flash_info,
|
||
|
|
ARRAY_SIZE(mityomapl138_spi_flash_info));
|
||
|
|
if (ret)
|
||
|
|
pr_warn("spi info registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
ret = da8xx_register_spi_bus(1,
|
||
|
|
ARRAY_SIZE(mityomapl138_spi_flash_info));
|
||
|
|
if (ret)
|
||
|
|
pr_warning("spi 1 registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
mityomapl138_config_emac();
|
||
|
|
|
||
|
|
ret = da8xx_register_rtc();
|
||
|
|
if (ret)
|
||
|
|
pr_warning("rtc setup failed: %d\n", ret);
|
||
|
|
|
||
|
|
ret = da8xx_register_cpuidle();
|
||
|
|
if (ret)
|
||
|
|
pr_warning("cpuidle registration failed: %d\n", ret);
|
||
|
|
|
||
|
|
ret = da850_register_pm(&da850_pm_device);
|
||
|
|
if (ret)
|
||
|
|
pr_warning("da850_evm_init: suspend registration failed: %d\n",
|
||
|
|
ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||
|
|
static int __init mityomapl138_console_init(void)
|
||
|
|
{
|
||
|
|
if (!machine_is_mityomapl138())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
return add_preferred_console("ttyS", 1, "115200");
|
||
|
|
}
|
||
|
|
console_initcall(mityomapl138_console_init);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static void __init mityomapl138_map_io(void)
|
||
|
|
{
|
||
|
|
da850_init();
|
||
|
|
}
|
||
|
|
|
||
|
|
MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
|
||
|
|
.atag_offset = 0x100,
|
||
|
|
.map_io = mityomapl138_map_io,
|
||
|
|
.init_irq = cp_intc_init,
|
||
|
|
.init_time = davinci_timer_init,
|
||
|
|
.init_machine = mityomapl138_init,
|
||
|
|
.init_late = davinci_init_late,
|
||
|
|
.dma_zone_size = SZ_128M,
|
||
|
|
.restart = da8xx_restart,
|
||
|
|
MACHINE_END
|