299 lines
8.2 KiB
C
299 lines
8.2 KiB
C
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/*
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* OMAP4+ Power Management Routines
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*
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* Copyright (C) 2010-2013 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <asm/system_misc.h>
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#include "soc.h"
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#include "common.h"
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#include "clockdomain.h"
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#include "powerdomain.h"
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#include "pm.h"
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u16 pm44xx_errata;
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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u32 next_logic_state;
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#ifdef CONFIG_SUSPEND
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u32 saved_state;
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u32 saved_logic_state;
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#endif
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struct list_head node;
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};
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static u32 cpu_suspend_state = PWRDM_POWER_OFF;
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static LIST_HEAD(pwrst_list);
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#ifdef CONFIG_SUSPEND
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static int omap4_pm_suspend(void)
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{
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struct power_state *pwrst;
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int state, ret = 0;
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u32 cpu_id = smp_processor_id();
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/* Save current powerdomain state */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
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pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
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}
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/* Set targeted power domain states by suspend */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
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pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
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}
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/*
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* For MPUSS to hit power domain retention(CSWR or OSWR),
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* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
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* since CPU power domain CSWR is not supported by hardware
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* Only master CPU follows suspend path. All other CPUs follow
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* CPU hotplug path in system wide suspend. On OMAP4, CPU power
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* domain CSWR is not supported by hardware.
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* More details can be found in OMAP4430 TRM section 4.3.4.2.
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*/
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omap4_enter_lowpower(cpu_id, cpu_suspend_state);
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/* Restore next powerdomain state */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
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if (state > pwrst->next_state) {
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pr_info("Powerdomain (%s) didn't enter target state %d\n",
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pwrst->pwrdm->name, pwrst->next_state);
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ret = -1;
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}
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omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
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pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
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}
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if (ret) {
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pr_crit("Could not enter target state in pm_suspend\n");
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/*
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* OMAP4 chip PM currently works only with certain (newer)
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* versions of bootloaders. This is due to missing code in the
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* kernel to properly reset and initialize some devices.
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* Warn the user about the bootloader version being one of the
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* possible causes.
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* http://www.spinics.net/lists/arm-kernel/msg218641.html
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*/
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pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
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} else {
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pr_info("Successfully put all powerdomains to target state\n");
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}
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return 0;
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}
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#else
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#define omap4_pm_suspend NULL
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#endif /* CONFIG_SUSPEND */
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static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
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{
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struct power_state *pwrst;
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if (!pwrdm->pwrsts)
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return 0;
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/*
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* Skip CPU0 and CPU1 power domains. CPU1 is programmed
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* through hotplug path and CPU0 explicitly programmed
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* further down in the code path
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*/
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if (!strncmp(pwrdm->name, "cpu", 3)) {
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if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
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cpu_suspend_state = PWRDM_POWER_RET;
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return 0;
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}
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pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
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if (!pwrst)
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return -ENOMEM;
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pwrst->pwrdm = pwrdm;
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pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
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PWRDM_POWER_RET);
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pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
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PWRDM_POWER_OFF);
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list_add(&pwrst->node, &pwrst_list);
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return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
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}
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/**
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* omap_default_idle - OMAP4 default ilde routine.'
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*
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* Implements OMAP4 memory, IO ordering requirements which can't be addressed
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* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
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* by secondary CPU with CONFIG_CPU_IDLE.
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*/
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static void omap_default_idle(void)
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{
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omap_do_wfi();
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}
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/**
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* omap4_init_static_deps - Add OMAP4 static dependencies
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*
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* Add needed static clockdomain dependencies on OMAP4 devices.
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* Return: 0 on success or 'err' on failures
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*/
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static inline int omap4_init_static_deps(void)
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{
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struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
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struct clockdomain *ducati_clkdm, *l3_2_clkdm;
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int ret = 0;
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/*
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* The dynamic dependency between MPUSS -> MEMIF and
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* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
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* expected. The hardware recommendation is to enable static
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* dependencies for these to avoid system lock ups or random crashes.
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* The L4 wakeup depedency is added to workaround the OCP sync hardware
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* BUG with 32K synctimer which lead to incorrect timer value read
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* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
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* are part of L4 wakeup clockdomain.
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*/
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mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
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emif_clkdm = clkdm_lookup("l3_emif_clkdm");
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l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
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l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
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ducati_clkdm = clkdm_lookup("ducati_clkdm");
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if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
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(!l3_2_clkdm) || (!ducati_clkdm))
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return -EINVAL;
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ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
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ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
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ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
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ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
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ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
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if (ret) {
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pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
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return -EINVAL;
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}
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return ret;
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}
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/**
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* omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
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* DRA7
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*
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* The dynamic dependency between MPUSS -> EMIF is broken and has
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* not worked as expected. The hardware recommendation is to
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* enable static dependencies for these to avoid system
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* lock ups or random crashes.
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*/
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static inline int omap5_dra7_init_static_deps(void)
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{
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struct clockdomain *mpuss_clkdm, *emif_clkdm;
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int ret;
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mpuss_clkdm = clkdm_lookup("mpu_clkdm");
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emif_clkdm = clkdm_lookup("emif_clkdm");
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if (!mpuss_clkdm || !emif_clkdm)
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return -EINVAL;
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ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
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if (ret)
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pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
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return ret;
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}
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/**
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* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
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*
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* Initializes basic stuff for power management functionality.
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*/
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int __init omap4_pm_init_early(void)
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{
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if (cpu_is_omap446x())
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pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
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if (soc_is_omap54xx() || soc_is_dra7xx())
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pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
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return 0;
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}
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/**
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* omap4_pm_init - Init routine for OMAP4+ devices
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*
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* Initializes all powerdomain and clockdomain target states
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* and all PRCM settings.
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* Return: Returns the error code returned by called functions.
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*/
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int __init omap4_pm_init(void)
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{
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int ret = 0;
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
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return -ENODEV;
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}
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pr_info("Power Management for TI OMAP4+ devices.\n");
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/*
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* OMAP4 chip PM currently works only with certain (newer)
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* versions of bootloaders. This is due to missing code in the
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* kernel to properly reset and initialize some devices.
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* http://www.spinics.net/lists/arm-kernel/msg218641.html
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*/
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if (cpu_is_omap44xx())
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pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
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ret = pwrdm_for_each(pwrdms_setup, NULL);
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if (ret) {
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pr_err("Failed to setup powerdomains.\n");
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goto err2;
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}
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if (cpu_is_omap44xx())
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ret = omap4_init_static_deps();
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else if (soc_is_omap54xx() || soc_is_dra7xx())
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ret = omap5_dra7_init_static_deps();
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if (ret) {
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pr_err("Failed to initialise static dependencies.\n");
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goto err2;
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}
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ret = omap4_mpuss_init();
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if (ret) {
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pr_err("Failed to initialise OMAP4 MPUSS\n");
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goto err2;
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}
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(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
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omap_common_suspend_init(omap4_pm_suspend);
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/* Overwrite the default cpu_do_idle() */
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arm_pm_idle = omap_default_idle;
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if (cpu_is_omap44xx())
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omap4_idle_init();
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err2:
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return ret;
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}
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