246 lines
6 KiB
C
246 lines
6 KiB
C
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/*
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* Copyright (C) 2010, 2011 Texas Instruments Incorporated
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* Contributed by: Mark Salter (msalter@redhat.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/soc.h>
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#include <asm/dscr.h>
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#include <asm/special_insns.h>
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#include <asm/timer64.h>
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struct timer_regs {
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u32 reserved0;
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u32 emumgt;
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u32 reserved1;
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u32 reserved2;
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u32 cntlo;
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u32 cnthi;
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u32 prdlo;
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u32 prdhi;
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u32 tcr;
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u32 tgcr;
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u32 wdtcr;
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};
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static struct timer_regs __iomem *timer;
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#define TCR_TSTATLO 0x001
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#define TCR_INVOUTPLO 0x002
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#define TCR_INVINPLO 0x004
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#define TCR_CPLO 0x008
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#define TCR_ENAMODELO_ONCE 0x040
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#define TCR_ENAMODELO_CONT 0x080
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#define TCR_ENAMODELO_MASK 0x0c0
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#define TCR_PWIDLO_MASK 0x030
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#define TCR_CLKSRCLO 0x100
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#define TCR_TIENLO 0x200
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#define TCR_TSTATHI (0x001 << 16)
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#define TCR_INVOUTPHI (0x002 << 16)
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#define TCR_CPHI (0x008 << 16)
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#define TCR_PWIDHI_MASK (0x030 << 16)
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#define TCR_ENAMODEHI_ONCE (0x040 << 16)
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#define TCR_ENAMODEHI_CONT (0x080 << 16)
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#define TCR_ENAMODEHI_MASK (0x0c0 << 16)
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#define TGCR_TIMLORS 0x001
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#define TGCR_TIMHIRS 0x002
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#define TGCR_TIMMODE_UD32 0x004
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#define TGCR_TIMMODE_WDT64 0x008
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#define TGCR_TIMMODE_CD32 0x00c
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#define TGCR_TIMMODE_MASK 0x00c
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#define TGCR_PSCHI_MASK (0x00f << 8)
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#define TGCR_TDDRHI_MASK (0x00f << 12)
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/*
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* Timer clocks are divided down from the CPU clock
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* The divisor is in the EMUMGTCLKSPD register
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*/
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#define TIMER_DIVISOR \
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((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
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#define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
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#define TIMER64_MODE_DISABLED 0
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#define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
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#define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
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static int timer64_mode;
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static int timer64_devstate_id = -1;
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static void timer64_config(unsigned long period)
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{
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u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
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soc_writel(tcr, &timer->tcr);
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soc_writel(period - 1, &timer->prdlo);
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soc_writel(0, &timer->cntlo);
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tcr |= timer64_mode;
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soc_writel(tcr, &timer->tcr);
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}
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static void timer64_enable(void)
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{
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u32 val;
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if (timer64_devstate_id >= 0)
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dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
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/* disable timer, reset count */
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soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
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soc_writel(0, &timer->prdlo);
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/* use internal clock and 1 cycle pulse width */
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val = soc_readl(&timer->tcr);
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soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
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/* dual 32-bit unchained mode */
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val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
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soc_writel(val, &timer->tgcr);
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soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
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}
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static void timer64_disable(void)
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{
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/* disable timer, reset count */
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soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
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soc_writel(0, &timer->prdlo);
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if (timer64_devstate_id >= 0)
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dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
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}
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static int next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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timer64_config(delta);
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return 0;
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}
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static void set_clock_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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timer64_enable();
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timer64_mode = TIMER64_MODE_PERIODIC;
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timer64_config(TIMER64_RATE / HZ);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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timer64_enable();
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timer64_mode = TIMER64_MODE_ONE_SHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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timer64_mode = TIMER64_MODE_DISABLED;
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timer64_disable();
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device t64_clockevent_device = {
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.name = "TIMER64_EVT32_TIMER",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.rating = 200,
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.set_mode = set_clock_mode,
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.set_next_event = next_event,
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};
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = &t64_clockevent_device;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction timer_iact = {
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.name = "timer",
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.flags = IRQF_TIMER,
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.handler = timer_interrupt,
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.dev_id = &t64_clockevent_device,
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};
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void __init timer64_init(void)
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{
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struct clock_event_device *cd = &t64_clockevent_device;
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struct device_node *np, *first = NULL;
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u32 val;
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int err, found = 0;
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for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
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err = of_property_read_u32(np, "ti,core-mask", &val);
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if (!err) {
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if (val & (1 << get_coreid())) {
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found = 1;
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break;
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}
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} else if (!first)
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first = np;
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}
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if (!found) {
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/* try first one with no core-mask */
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if (first)
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np = of_node_get(first);
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else {
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pr_debug("Cannot find ti,c64x+timer64 timer.\n");
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return;
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}
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}
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timer = of_iomap(np, 0);
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if (!timer) {
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pr_debug("%s: Cannot map timer registers.\n", np->full_name);
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goto out;
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}
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pr_debug("%s: Timer registers=%p.\n", np->full_name, timer);
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cd->irq = irq_of_parse_and_map(np, 0);
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if (cd->irq == NO_IRQ) {
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pr_debug("%s: Cannot find interrupt.\n", np->full_name);
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iounmap(timer);
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goto out;
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}
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/* If there is a device state control, save the ID. */
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err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
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if (!err) {
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timer64_devstate_id = val;
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/*
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* It is necessary to enable the timer block here because
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* the TIMER_DIVISOR macro needs to read a timer register
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* to get the divisor.
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*/
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dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
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}
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pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq);
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clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(250, cd);
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cd->cpumask = cpumask_of(smp_processor_id());
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clockevents_register_device(cd);
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setup_irq(cd->irq, &timer_iact);
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out:
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of_node_put(np);
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return;
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}
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