667 lines
16 KiB
C
667 lines
16 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
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* Copyright (C) 2001 MIPS Technologies, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/module.h>
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#include <asm/branch.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/fpu.h>
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#include <asm/fpu_emulator.h>
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#include <asm/inst.h>
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#include <asm/ptrace.h>
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#include <asm/uaccess.h>
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/*
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* Calculate and return exception PC in case of branch delay slot
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* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
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*/
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int __isa_exception_epc(struct pt_regs *regs)
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{
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unsigned short inst;
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long epc = regs->cp0_epc;
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/* Calculate exception PC in branch delay slot. */
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if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
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/* This should never happen because delay slot was checked. */
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force_sig(SIGSEGV, current);
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return epc;
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}
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if (cpu_has_mips16) {
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if (((union mips16e_instruction)inst).ri.opcode
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== MIPS16e_jal_op)
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epc += 4;
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else
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epc += 2;
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} else if (mm_insn_16bit(inst))
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epc += 2;
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else
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epc += 4;
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return epc;
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}
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/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
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static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
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int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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unsigned long *contpc)
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{
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union mips_instruction insn = (union mips_instruction)dec_insn.insn;
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int bc_false = 0;
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unsigned int fcr31;
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unsigned int bit;
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if (!cpu_has_mmips)
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return 0;
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switch (insn.mm_i_format.opcode) {
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case mm_pool32a_op:
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if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
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mm_pool32axf_op) {
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switch (insn.mm_i_format.simmediate >>
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MM_POOL32A_MINOR_SHIFT) {
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case mm_jalr_op:
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case mm_jalrhb_op:
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case mm_jalrs_op:
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case mm_jalrshb_op:
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if (insn.mm_i_format.rt != 0) /* Not mm_jr */
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regs->regs[insn.mm_i_format.rt] =
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regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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*contpc = regs->regs[insn.mm_i_format.rs];
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return 1;
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}
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}
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break;
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case mm_pool32i_op:
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switch (insn.mm_i_format.rt) {
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case mm_bltzals_op:
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case mm_bltzal_op:
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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/* Fall through */
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case mm_bltz_op:
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if ((long)regs->regs[insn.mm_i_format.rs] < 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case mm_bgezals_op:
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case mm_bgezal_op:
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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/* Fall through */
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case mm_bgez_op:
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if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case mm_blez_op:
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if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case mm_bgtz_op:
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if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case mm_bc2f_op:
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case mm_bc1f_op:
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bc_false = 1;
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/* Fall through */
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case mm_bc2t_op:
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case mm_bc1t_op:
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preempt_disable();
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if (is_fpu_owner())
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fcr31 = read_32bit_cp1_register(CP1_STATUS);
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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if (bc_false)
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fcr31 = ~fcr31;
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bit = (insn.mm_i_format.rs >> 2);
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bit += (bit != 0);
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bit += 23;
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if (fcr31 & (1 << bit))
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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return 1;
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}
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break;
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case mm_pool16c_op:
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switch (insn.mm_i_format.rt) {
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case mm_jalr16_op:
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case mm_jalrs16_op:
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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/* Fall through */
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case mm_jr16_op:
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*contpc = regs->regs[insn.mm_i_format.rs];
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return 1;
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}
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break;
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case mm_beqz16_op:
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if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_b1_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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return 1;
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case mm_bnez16_op:
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if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_b1_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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return 1;
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case mm_b16_op:
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*contpc = regs->cp0_epc + dec_insn.pc_inc +
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(insn.mm_b0_format.simmediate << 1);
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return 1;
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case mm_beq32_op:
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if (regs->regs[insn.mm_i_format.rs] ==
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regs->regs[insn.mm_i_format.rt])
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case mm_bne32_op:
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if (regs->regs[insn.mm_i_format.rs] !=
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regs->regs[insn.mm_i_format.rt])
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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(insn.mm_i_format.simmediate << 1);
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else
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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return 1;
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case mm_jalx32_op:
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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*contpc = regs->cp0_epc + dec_insn.pc_inc;
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*contpc >>= 28;
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*contpc <<= 28;
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*contpc |= (insn.j_format.target << 2);
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return 1;
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case mm_jals32_op:
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case mm_jal32_op:
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc + dec_insn.next_pc_inc;
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/* Fall through */
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case mm_j32_op:
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*contpc = regs->cp0_epc + dec_insn.pc_inc;
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*contpc >>= 27;
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*contpc <<= 27;
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*contpc |= (insn.j_format.target << 1);
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set_isa16_mode(*contpc);
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return 1;
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}
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return 0;
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}
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/*
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* Compute return address and emulate branch in microMIPS mode after an
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* exception only. It does not handle compact branches/jumps and cannot
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* be used in interrupt context. (Compact branches/jumps do not cause
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* exceptions.)
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*/
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int __microMIPS_compute_return_epc(struct pt_regs *regs)
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{
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u16 __user *pc16;
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u16 halfword;
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unsigned int word;
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unsigned long contpc;
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struct mm_decoded_insn mminsn = { 0 };
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mminsn.micro_mips_mode = 1;
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/* This load never faults. */
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pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
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__get_user(halfword, pc16);
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pc16++;
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contpc = regs->cp0_epc + 2;
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word = ((unsigned int)halfword << 16);
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mminsn.pc_inc = 2;
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if (!mm_insn_16bit(halfword)) {
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__get_user(halfword, pc16);
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pc16++;
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contpc = regs->cp0_epc + 4;
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mminsn.pc_inc = 4;
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word |= halfword;
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}
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mminsn.insn = word;
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if (get_user(halfword, pc16))
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goto sigsegv;
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mminsn.next_pc_inc = 2;
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word = ((unsigned int)halfword << 16);
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if (!mm_insn_16bit(halfword)) {
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pc16++;
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if (get_user(halfword, pc16))
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goto sigsegv;
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mminsn.next_pc_inc = 4;
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word |= halfword;
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}
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mminsn.next_insn = word;
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mm_isBranchInstr(regs, mminsn, &contpc);
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regs->cp0_epc = contpc;
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return 0;
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sigsegv:
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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/*
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* Compute return address and emulate branch in MIPS16e mode after an
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* exception only. It does not handle compact branches/jumps and cannot
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* be used in interrupt context. (Compact branches/jumps do not cause
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* exceptions.)
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*/
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int __MIPS16e_compute_return_epc(struct pt_regs *regs)
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{
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u16 __user *addr;
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union mips16e_instruction inst;
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u16 inst2;
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u32 fullinst;
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long epc;
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epc = regs->cp0_epc;
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/* Read the instruction. */
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addr = (u16 __user *)msk_isa16_mode(epc);
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if (__get_user(inst.full, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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switch (inst.ri.opcode) {
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case MIPS16e_extend_op:
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regs->cp0_epc += 4;
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return 0;
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/*
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* JAL and JALX in MIPS16e mode
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*/
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case MIPS16e_jal_op:
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addr += 1;
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if (__get_user(inst2, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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fullinst = ((unsigned)inst.full << 16) | inst2;
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regs->regs[31] = epc + 6;
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epc += 4;
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epc >>= 28;
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epc <<= 28;
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/*
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* JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
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*
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* ......TARGET[15:0].................TARGET[20:16]...........
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* ......TARGET[25:21]
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*/
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epc |=
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((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
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((fullinst & 0x1f0000) << 7);
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||
|
|
if (!inst.jal.x)
|
||
|
|
set_isa16_mode(epc); /* Set ISA mode bit. */
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* J(AL)R(C)
|
||
|
|
*/
|
||
|
|
case MIPS16e_rr_op:
|
||
|
|
if (inst.rr.func == MIPS16e_jr_func) {
|
||
|
|
|
||
|
|
if (inst.rr.ra)
|
||
|
|
regs->cp0_epc = regs->regs[31];
|
||
|
|
else
|
||
|
|
regs->cp0_epc =
|
||
|
|
regs->regs[reg16to32[inst.rr.rx]];
|
||
|
|
|
||
|
|
if (inst.rr.l) {
|
||
|
|
if (inst.rr.nd)
|
||
|
|
regs->regs[31] = epc + 2;
|
||
|
|
else
|
||
|
|
regs->regs[31] = epc + 4;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* All other cases have no branch delay slot and are 16-bits.
|
||
|
|
* Branches do not cause an exception.
|
||
|
|
*/
|
||
|
|
regs->cp0_epc += 2;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* __compute_return_epc_for_insn - Computes the return address and do emulate
|
||
|
|
* branch simulation, if required.
|
||
|
|
*
|
||
|
|
* @regs: Pointer to pt_regs
|
||
|
|
* @insn: branch instruction to decode
|
||
|
|
* @returns: -EFAULT on error and forces SIGBUS, and on success
|
||
|
|
* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
|
||
|
|
* evaluating the branch.
|
||
|
|
*/
|
||
|
|
int __compute_return_epc_for_insn(struct pt_regs *regs,
|
||
|
|
union mips_instruction insn)
|
||
|
|
{
|
||
|
|
unsigned int bit, fcr31, dspcontrol;
|
||
|
|
long epc = regs->cp0_epc;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
switch (insn.i_format.opcode) {
|
||
|
|
/*
|
||
|
|
* jr and jalr are in r_format format.
|
||
|
|
*/
|
||
|
|
case spec_op:
|
||
|
|
switch (insn.r_format.func) {
|
||
|
|
case jalr_op:
|
||
|
|
regs->regs[insn.r_format.rd] = epc + 8;
|
||
|
|
/* Fall through */
|
||
|
|
case jr_op:
|
||
|
|
regs->cp0_epc = regs->regs[insn.r_format.rs];
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This group contains:
|
||
|
|
* bltz_op, bgez_op, bltzl_op, bgezl_op,
|
||
|
|
* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
|
||
|
|
*/
|
||
|
|
case bcond_op:
|
||
|
|
switch (insn.i_format.rt) {
|
||
|
|
case bltz_op:
|
||
|
|
case bltzl_op:
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] < 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == bltzl_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bgez_op:
|
||
|
|
case bgezl_op:
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] >= 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == bgezl_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bltzal_op:
|
||
|
|
case bltzall_op:
|
||
|
|
regs->regs[31] = epc + 8;
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] < 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == bltzall_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bgezal_op:
|
||
|
|
case bgezall_op:
|
||
|
|
regs->regs[31] = epc + 8;
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] >= 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == bgezall_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bposge32_op:
|
||
|
|
if (!cpu_has_dsp)
|
||
|
|
goto sigill;
|
||
|
|
|
||
|
|
dspcontrol = rddsp(0x01);
|
||
|
|
|
||
|
|
if (dspcontrol >= 32) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* These are unconditional and in j_format.
|
||
|
|
*/
|
||
|
|
case jal_op:
|
||
|
|
regs->regs[31] = regs->cp0_epc + 8;
|
||
|
|
case j_op:
|
||
|
|
epc += 4;
|
||
|
|
epc >>= 28;
|
||
|
|
epc <<= 28;
|
||
|
|
epc |= (insn.j_format.target << 2);
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
if (insn.i_format.opcode == jalx_op)
|
||
|
|
set_isa16_mode(regs->cp0_epc);
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* These are conditional and in i_format.
|
||
|
|
*/
|
||
|
|
case beq_op:
|
||
|
|
case beql_op:
|
||
|
|
if (regs->regs[insn.i_format.rs] ==
|
||
|
|
regs->regs[insn.i_format.rt]) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.opcode == beql_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bne_op:
|
||
|
|
case bnel_op:
|
||
|
|
if (regs->regs[insn.i_format.rs] !=
|
||
|
|
regs->regs[insn.i_format.rt]) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.opcode == bnel_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case blez_op: /* not really i_format */
|
||
|
|
case blezl_op:
|
||
|
|
/* rt field assumed to be zero */
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] <= 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.opcode == blezl_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case bgtz_op:
|
||
|
|
case bgtzl_op:
|
||
|
|
/* rt field assumed to be zero */
|
||
|
|
if ((long)regs->regs[insn.i_format.rs] > 0) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.opcode == bgtzl_op)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* And now the FPA/cp1 branch instructions.
|
||
|
|
*/
|
||
|
|
case cop1_op:
|
||
|
|
preempt_disable();
|
||
|
|
if (is_fpu_owner())
|
||
|
|
fcr31 = read_32bit_cp1_register(CP1_STATUS);
|
||
|
|
else
|
||
|
|
fcr31 = current->thread.fpu.fcr31;
|
||
|
|
preempt_enable();
|
||
|
|
|
||
|
|
bit = (insn.i_format.rt >> 2);
|
||
|
|
bit += (bit != 0);
|
||
|
|
bit += 23;
|
||
|
|
switch (insn.i_format.rt & 3) {
|
||
|
|
case 0: /* bc1f */
|
||
|
|
case 2: /* bc1fl */
|
||
|
|
if (~fcr31 & (1 << bit)) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == 2)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 1: /* bc1t */
|
||
|
|
case 3: /* bc1tl */
|
||
|
|
if (fcr31 & (1 << bit)) {
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
if (insn.i_format.rt == 3)
|
||
|
|
ret = BRANCH_LIKELY_TAKEN;
|
||
|
|
} else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||
|
|
case lwc2_op: /* This is bbit0 on Octeon */
|
||
|
|
if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
|
||
|
|
== 0)
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
case ldc2_op: /* This is bbit032 on Octeon */
|
||
|
|
if ((regs->regs[insn.i_format.rs] &
|
||
|
|
(1ull<<(insn.i_format.rt+32))) == 0)
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
case swc2_op: /* This is bbit1 on Octeon */
|
||
|
|
if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
case sdc2_op: /* This is bbit132 on Octeon */
|
||
|
|
if (regs->regs[insn.i_format.rs] &
|
||
|
|
(1ull<<(insn.i_format.rt+32)))
|
||
|
|
epc = epc + 4 + (insn.i_format.simmediate << 2);
|
||
|
|
else
|
||
|
|
epc += 8;
|
||
|
|
regs->cp0_epc = epc;
|
||
|
|
break;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
sigill:
|
||
|
|
printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
|
||
|
|
force_sig(SIGBUS, current);
|
||
|
|
return -EFAULT;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
|
||
|
|
|
||
|
|
int __compute_return_epc(struct pt_regs *regs)
|
||
|
|
{
|
||
|
|
unsigned int __user *addr;
|
||
|
|
long epc;
|
||
|
|
union mips_instruction insn;
|
||
|
|
|
||
|
|
epc = regs->cp0_epc;
|
||
|
|
if (epc & 3)
|
||
|
|
goto unaligned;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Read the instruction
|
||
|
|
*/
|
||
|
|
addr = (unsigned int __user *) epc;
|
||
|
|
if (__get_user(insn.word, addr)) {
|
||
|
|
force_sig(SIGSEGV, current);
|
||
|
|
return -EFAULT;
|
||
|
|
}
|
||
|
|
|
||
|
|
return __compute_return_epc_for_insn(regs, insn);
|
||
|
|
|
||
|
|
unaligned:
|
||
|
|
printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
|
||
|
|
force_sig(SIGBUS, current);
|
||
|
|
return -EFAULT;
|
||
|
|
}
|