399 lines
14 KiB
C
399 lines
14 KiB
C
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* provides masks and opcode images for use by code generation, emulation
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* and for instructions that older assemblers might not know about
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*/
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#ifndef _ASM_POWERPC_PPC_OPCODE_H
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#define _ASM_POWERPC_PPC_OPCODE_H
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#include <linux/stringify.h>
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#include <asm/asm-compat.h>
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#define __REG_R0 0
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#define __REG_R1 1
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#define __REG_R2 2
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#define __REG_R3 3
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#define __REG_R4 4
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#define __REG_R5 5
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#define __REG_R6 6
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#define __REG_R7 7
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#define __REG_R8 8
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#define __REG_R9 9
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#define __REG_R10 10
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#define __REG_R11 11
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#define __REG_R12 12
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#define __REG_R13 13
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#define __REG_R14 14
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#define __REG_R15 15
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#define __REG_R16 16
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#define __REG_R17 17
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#define __REG_R18 18
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#define __REG_R19 19
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#define __REG_R20 20
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#define __REG_R21 21
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#define __REG_R22 22
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#define __REG_R23 23
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#define __REG_R24 24
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#define __REG_R25 25
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#define __REG_R26 26
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#define __REG_R27 27
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#define __REG_R28 28
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#define __REG_R29 29
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#define __REG_R30 30
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#define __REG_R31 31
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#define __REGA0_0 0
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#define __REGA0_R1 1
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#define __REGA0_R2 2
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#define __REGA0_R3 3
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#define __REGA0_R4 4
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#define __REGA0_R5 5
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#define __REGA0_R6 6
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#define __REGA0_R7 7
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#define __REGA0_R8 8
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#define __REGA0_R9 9
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#define __REGA0_R10 10
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#define __REGA0_R11 11
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#define __REGA0_R12 12
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#define __REGA0_R13 13
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#define __REGA0_R14 14
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#define __REGA0_R15 15
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#define __REGA0_R16 16
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#define __REGA0_R17 17
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#define __REGA0_R18 18
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#define __REGA0_R19 19
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#define __REGA0_R20 20
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#define __REGA0_R21 21
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#define __REGA0_R22 22
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#define __REGA0_R23 23
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#define __REGA0_R24 24
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#define __REGA0_R25 25
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#define __REGA0_R26 26
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#define __REGA0_R27 27
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#define __REGA0_R28 28
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#define __REGA0_R29 29
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#define __REGA0_R30 30
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#define __REGA0_R31 31
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/* opcode and xopcode for instructions */
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#define OP_TRAP 3
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#define OP_TRAP_64 2
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#define OP_31_XOP_TRAP 4
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#define OP_31_XOP_LWZX 23
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#define OP_31_XOP_DCBST 54
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#define OP_31_XOP_LWZUX 55
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#define OP_31_XOP_TRAP_64 68
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#define OP_31_XOP_DCBF 86
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#define OP_31_XOP_LBZX 87
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#define OP_31_XOP_STWX 151
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#define OP_31_XOP_STBX 215
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#define OP_31_XOP_LBZUX 119
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#define OP_31_XOP_STBUX 247
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#define OP_31_XOP_LHZX 279
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#define OP_31_XOP_LHZUX 311
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#define OP_31_XOP_MFSPR 339
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#define OP_31_XOP_LHAX 343
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#define OP_31_XOP_LHAUX 375
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#define OP_31_XOP_STHX 407
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#define OP_31_XOP_STHUX 439
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#define OP_31_XOP_MTSPR 467
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#define OP_31_XOP_DCBI 470
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#define OP_31_XOP_LWBRX 534
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#define OP_31_XOP_TLBSYNC 566
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#define OP_31_XOP_STWBRX 662
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#define OP_31_XOP_LHBRX 790
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#define OP_31_XOP_STHBRX 918
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#define OP_LWZ 32
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#define OP_LD 58
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#define OP_LWZU 33
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#define OP_LBZ 34
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#define OP_LBZU 35
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#define OP_STW 36
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#define OP_STWU 37
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#define OP_STD 62
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#define OP_STB 38
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#define OP_STBU 39
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#define OP_LHZ 40
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#define OP_LHZU 41
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#define OP_LHA 42
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#define OP_LHAU 43
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#define OP_STH 44
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#define OP_STHU 45
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/* sorted alphabetically */
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#define PPC_INST_BHRBE 0x7c00025c
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#define PPC_INST_CLRBHRB 0x7c00035c
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#define PPC_INST_DCBA 0x7c0005ec
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#define PPC_INST_DCBA_MASK 0xfc0007fe
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#define PPC_INST_DCBAL 0x7c2005ec
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#define PPC_INST_DCBZL 0x7c2007ec
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#define PPC_INST_ICBT 0x7c00002c
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_LDARX 0x7c0000a8
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#define PPC_INST_LOGMPP 0x7c0007e4
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#define PPC_INST_LSWI 0x7c0004aa
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#define PPC_INST_LSWX 0x7c00042a
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#define PPC_INST_LWARX 0x7c000028
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#define PPC_INST_LWSYNC 0x7c2004ac
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#define PPC_INST_SYNC 0x7c0004ac
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#define PPC_INST_SYNC_MASK 0xfc0007fe
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#define PPC_INST_LXVD2X 0x7c000698
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#define PPC_INST_MCRXR 0x7c000400
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#define PPC_INST_MCRXR_MASK 0xfc0007fe
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#define PPC_INST_MFSPR_PVR 0x7c1f42a6
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#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
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#define PPC_INST_MFTMR 0x7c0002dc
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#define PPC_INST_MSGSND 0x7c00019c
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#define PPC_INST_MSGSNDP 0x7c00011c
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#define PPC_INST_MTTMR 0x7c0003dc
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#define PPC_INST_NOP 0x60000000
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#define PPC_INST_POPCNTB 0x7c0000f4
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#define PPC_INST_POPCNTB_MASK 0xfc0007fe
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#define PPC_INST_POPCNTD 0x7c0003f4
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#define PPC_INST_POPCNTW 0x7c0002f4
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#define PPC_INST_RFCI 0x4c000066
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#define PPC_INST_RFDI 0x4c00004e
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#define PPC_INST_RFMCI 0x4c00004c
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#define PPC_INST_MFSPR_DSCR 0x7c1102a6
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#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
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#define PPC_INST_MTSPR_DSCR 0x7c1103a6
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#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
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#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
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#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
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#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
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#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
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#define PPC_INST_SLBFEE 0x7c0007a7
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#define PPC_INST_STRING 0x7c00042a
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#define PPC_INST_STRING_MASK 0xfc0007fe
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#define PPC_INST_STRING_GEN_MASK 0xfc00067e
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#define PPC_INST_STSWI 0x7c0005aa
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#define PPC_INST_STSWX 0x7c00052a
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#define PPC_INST_STXVD2X 0x7c000798
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#define PPC_INST_TLBIE 0x7c000264
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#define PPC_INST_TLBILX 0x7c000024
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#define PPC_INST_WAIT 0x7c00007c
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#define PPC_INST_TLBIVAX 0x7c000624
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#define PPC_INST_TLBSRX_DOT 0x7c0006a5
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#define PPC_INST_XXLOR 0xf0000510
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#define PPC_INST_XXSWAPD 0xf0000250
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#define PPC_INST_XVCPSGNDP 0xf0000780
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#define PPC_INST_TRECHKPT 0x7c0007dd
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#define PPC_INST_TRECLAIM 0x7c00075d
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#define PPC_INST_TABORT 0x7c00071d
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#define PPC_INST_NAP 0x4c000364
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#define PPC_INST_SLEEP 0x4c0003a4
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/* A2 specific instructions */
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#define PPC_INST_ERATWE 0x7c0001a6
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#define PPC_INST_ERATRE 0x7c000166
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#define PPC_INST_ERATILX 0x7c000066
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#define PPC_INST_ERATIVAX 0x7c000666
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#define PPC_INST_ERATSX 0x7c000126
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#define PPC_INST_ERATSX_DOT 0x7c000127
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/* Misc instructions for BPF compiler */
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#define PPC_INST_LD 0xe8000000
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#define PPC_INST_LHZ 0xa0000000
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#define PPC_INST_LHBRX 0x7c00062c
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#define PPC_INST_LWZ 0x80000000
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#define PPC_INST_STD 0xf8000000
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#define PPC_INST_STDU 0xf8000001
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#define PPC_INST_MFLR 0x7c0802a6
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#define PPC_INST_MTLR 0x7c0803a6
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#define PPC_INST_CMPWI 0x2c000000
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#define PPC_INST_CMPDI 0x2c200000
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#define PPC_INST_CMPLW 0x7c000040
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#define PPC_INST_CMPLWI 0x28000000
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#define PPC_INST_ADDI 0x38000000
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#define PPC_INST_ADDIS 0x3c000000
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#define PPC_INST_ADD 0x7c000214
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#define PPC_INST_SUB 0x7c000050
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#define PPC_INST_BLR 0x4e800020
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#define PPC_INST_BLRL 0x4e800021
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#define PPC_INST_MULLW 0x7c0001d6
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#define PPC_INST_MULHWU 0x7c000016
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#define PPC_INST_MULLI 0x1c000000
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#define PPC_INST_DIVWU 0x7c000396
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#define PPC_INST_RLWINM 0x54000000
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#define PPC_INST_RLDICR 0x78000004
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#define PPC_INST_SLW 0x7c000030
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#define PPC_INST_SRW 0x7c000430
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#define PPC_INST_AND 0x7c000038
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#define PPC_INST_ANDDOT 0x7c000039
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#define PPC_INST_OR 0x7c000378
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#define PPC_INST_XOR 0x7c000278
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#define PPC_INST_ANDI 0x70000000
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#define PPC_INST_ORI 0x60000000
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#define PPC_INST_ORIS 0x64000000
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#define PPC_INST_XORI 0x68000000
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#define PPC_INST_XORIS 0x6c000000
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#define PPC_INST_NEG 0x7c0000d0
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#define PPC_INST_BRANCH 0x48000000
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#define PPC_INST_BRANCH_COND 0x40800000
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#define PPC_INST_LBZCIX 0x7c0006aa
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#define PPC_INST_STBCIX 0x7c0007aa
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/* macros to insert fields into opcodes */
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#define ___PPC_RA(a) (((a) & 0x1f) << 16)
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#define ___PPC_RB(b) (((b) & 0x1f) << 11)
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#define ___PPC_RS(s) (((s) & 0x1f) << 21)
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#define ___PPC_RT(t) ___PPC_RS(t)
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#define __PPC_RA(a) ___PPC_RA(__REG_##a)
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#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
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#define __PPC_RB(b) ___PPC_RB(__REG_##b)
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#define __PPC_RS(s) ___PPC_RS(__REG_##s)
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#define __PPC_RT(t) ___PPC_RT(__REG_##t)
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#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
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#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
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#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
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#define __PPC_XT(s) __PPC_XS(s)
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#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
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#define __PPC_WC(w) (((w) & 0x3) << 21)
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#define __PPC_WS(w) (((w) & 0x1f) << 11)
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#define __PPC_SH(s) __PPC_WS(s)
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#define __PPC_MB(s) (((s) & 0x1f) << 6)
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#define __PPC_ME(s) (((s) & 0x1f) << 1)
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#define __PPC_BI(s) (((s) & 0x1f) << 16)
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#define __PPC_CT(t) (((t) & 0x0f) << 21)
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* larx with EH set as an illegal instruction.
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*/
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#ifdef CONFIG_PPC64
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#define __PPC_EH(eh) (((eh) & 0x1) << 0)
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#else
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#define __PPC_EH(eh) 0
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#endif
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/* POWER8 Micro Partition Prefetch (MPP) parameters */
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/* Address mask is common for LOGMPP instruction and MPPR SPR */
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#define PPC_MPPE_ADDRESS_MASK 0xffffffffc000
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/* Bits 60 and 61 of MPP SPR should be set to one of the following */
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/* Aborting the fetch is indeed setting 00 in the table size bits */
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#define PPC_MPPR_FETCH_ABORT (0x0ULL << 60)
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#define PPC_MPPR_FETCH_WHOLE_TABLE (0x2ULL << 60)
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/* Bits 54 and 55 of register for LOGMPP instruction should be set to: */
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#define PPC_LOGMPP_LOG_L2 (0x02ULL << 54)
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#define PPC_LOGMPP_LOG_L2L3 (0x01ULL << 54)
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#define PPC_LOGMPP_LOG_ABORT (0x03ULL << 54)
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/* Deal with instructions that older assemblers aren't aware of */
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#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_LOGMPP(b) stringify_in_c(.long PPC_INST_LOGMPP | \
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__PPC_RB(b))
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#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
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___PPC_RB(b))
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#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
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___PPC_RB(b))
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#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
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#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
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#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
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#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
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__PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
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#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
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#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
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#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
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#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
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__PPC_WC(w))
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#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
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___PPC_RB(a) | ___PPC_RS(lp))
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#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
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__PPC_RA0(a) | __PPC_RB(b))
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#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
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__PPC_RA0(a) | __PPC_RB(b))
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#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
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__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
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__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
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__PPC_T_TLB(t) | __PPC_RA0(a) | \
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__PPC_RB(b))
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#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
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__PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
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#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
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__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
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#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
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__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
|
||
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#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
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|
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__PPC_RT(t) | __PPC_RB(b))
|
||
|
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#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
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||
|
|
__PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
|
||
|
|
/* PASemi instructions */
|
||
|
|
#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
|
||
|
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__PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
|
||
|
|
#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
|
||
|
|
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Define what the VSX XX1 form instructions will look like, then add
|
||
|
|
* the 128 bit load store instructions based on that.
|
||
|
|
*/
|
||
|
|
#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
|
||
|
|
#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
|
||
|
|
#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
|
||
|
|
VSX_XX1((s), a, b))
|
||
|
|
#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
|
||
|
|
VSX_XX1((s), a, b))
|
||
|
|
#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
|
||
|
|
VSX_XX3((t), a, b))
|
||
|
|
#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
|
||
|
|
VSX_XX3((t), a, a))
|
||
|
|
#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
|
||
|
|
VSX_XX3((t), (a), (b))))
|
||
|
|
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|
|
#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
|
||
|
|
#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
|
||
|
|
|
||
|
|
/* BHRB instructions */
|
||
|
|
#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
|
||
|
|
#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
|
||
|
|
__PPC_RT(r) | \
|
||
|
|
(((n) & 0x3ff) << 11))
|
||
|
|
|
||
|
|
/* Transactional memory instructions */
|
||
|
|
#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
|
||
|
|
#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
|
||
|
|
| __PPC_RA(r))
|
||
|
|
#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
|
||
|
|
| __PPC_RA(r))
|
||
|
|
|
||
|
|
/* book3e thread control instructions */
|
||
|
|
#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
|
||
|
|
#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \
|
||
|
|
TMRN(tmr) | ___PPC_RS(r))
|
||
|
|
#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \
|
||
|
|
TMRN(tmr) | ___PPC_RT(r))
|
||
|
|
|
||
|
|
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
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