160 lines
3.9 KiB
ArmAsm
160 lines
3.9 KiB
ArmAsm
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* arch/shmedia/boot/compressed/head.S
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*
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* Copied from
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* arch/shmedia/kernel/head.S
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* which carried the copyright:
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* Copyright (C) 2000, 2001 Paolo Alberelli
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*
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* Modification for compressed loader:
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* Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com)
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*/
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#include <asm/cache.h>
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#include <asm/tlb.h>
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#include <cpu/mmu_context.h>
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#include <cpu/registers.h>
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/*
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* Fixed TLB entries to identity map the beginning of RAM
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*/
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#define MMUIR_TEXT_H 0x0000000000000003 | CONFIG_MEMORY_START
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/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
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#define MMUIR_TEXT_L 0x000000000000009a | CONFIG_MEMORY_START
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/* 512 Mb, Cacheable (Write-back), execute, Not User, Ph. Add. */
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#define MMUDR_CACHED_H 0x0000000000000003 | CONFIG_MEMORY_START
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/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
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#define MMUDR_CACHED_L 0x000000000000015a | CONFIG_MEMORY_START
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/* 512 Mb, Cacheable (Write-back), read/write, Not User, Ph. Add. */
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#define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */
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#define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */
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#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* OCE + OCI + WB */
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#define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */
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.text
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.global startup
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startup:
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/*
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* Prevent speculative fetch on device memory due to
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* uninitialized target registers.
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* This must be executed before the first branch.
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*/
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ptabs/u r63, tr0
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ptabs/u r63, tr1
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ptabs/u r63, tr2
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ptabs/u r63, tr3
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ptabs/u r63, tr4
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ptabs/u r63, tr5
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ptabs/u r63, tr6
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ptabs/u r63, tr7
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synci
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/*
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* Set initial TLB entries for cached and uncached regions.
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* Note: PTA/BLINK is PIC code, PTABS/BLINK isn't !
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*/
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/* Clear ITLBs */
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pta 1f, tr1
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movi ITLB_FIXED, r21
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movi ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
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1: putcfg r21, 0, r63 /* Clear MMUIR[n].PTEH.V */
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addi r21, TLB_STEP, r21
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bne r21, r22, tr1
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/* Clear DTLBs */
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pta 1f, tr1
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movi DTLB_FIXED, r21
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movi DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
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1: putcfg r21, 0, r63 /* Clear MMUDR[n].PTEH.V */
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addi r21, TLB_STEP, r21
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bne r21, r22, tr1
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/* Map one big (512Mb) page for ITLB */
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movi ITLB_FIXED, r21
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movi MMUIR_TEXT_L, r22 /* PTEL first */
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putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
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movi MMUIR_TEXT_H, r22 /* PTEH last */
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putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
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/* Map one big CACHED (512Mb) page for DTLB */
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movi DTLB_FIXED, r21
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movi MMUDR_CACHED_L, r22 /* PTEL first */
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putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
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movi MMUDR_CACHED_H, r22 /* PTEH last */
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putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
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/* ICache */
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movi ICCR_BASE, r21
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movi ICCR0_INIT_VAL, r22
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movi ICCR1_INIT_VAL, r23
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putcfg r21, ICCR_REG0, r22
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putcfg r21, ICCR_REG1, r23
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synci
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/* OCache */
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movi OCCR_BASE, r21
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movi OCCR0_INIT_VAL, r22
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movi OCCR1_INIT_VAL, r23
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putcfg r21, OCCR_REG0, r22
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putcfg r21, OCCR_REG1, r23
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synco
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/*
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* Enable the MMU.
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* From here-on code can be non-PIC.
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*/
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movi SR_HARMLESS | SR_ENABLE_MMU, r22
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putcon r22, SSR
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movi 1f, r22
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putcon r22, SPC
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synco
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rte /* And now go into the hyperspace ... */
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1: /* ... that's the next instruction ! */
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/* Set initial stack pointer */
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movi datalabel stack_start, r0
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ld.l r0, 0, r15
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/*
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* Clear bss
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*/
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pt 1f, tr1
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movi datalabel __bss_start, r22
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movi datalabel _end, r23
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1: st.l r22, 0, r63
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addi r22, 4, r22
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bne r22, r23, tr1
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/*
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* Decompress the kernel.
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*/
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pt decompress_kernel, tr0
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blink tr0, r18
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/*
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* Disable the MMU.
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*/
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movi SR_HARMLESS, r22
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putcon r22, SSR
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movi 1f, r22
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putcon r22, SPC
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synco
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rte /* And now go into the hyperspace ... */
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1: /* ... that's the next instruction ! */
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/* Jump into the decompressed kernel */
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movi datalabel (CONFIG_MEMORY_START + 0x2000)+1, r19
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ptabs r19, tr0
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blink tr0, r18
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/* Shouldn't return here, but just in case, loop forever */
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pt 1f, tr0
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1: blink tr0, r63
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