514 lines
15 KiB
C
514 lines
15 KiB
C
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/*
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* linux/drivers/pinctrl/pinmux-falcon.c
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* based on linux/drivers/pinctrl/pinmux-pxa910.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include "pinctrl-lantiq.h"
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#include <lantiq_soc.h>
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/* Multiplexer Control Register */
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#define LTQ_PADC_MUX(x) (x * 0x4)
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/* Pull Up Enable Register */
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#define LTQ_PADC_PUEN 0x80
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/* Pull Down Enable Register */
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#define LTQ_PADC_PDEN 0x84
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/* Slew Rate Control Register */
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#define LTQ_PADC_SRC 0x88
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/* Drive Current Control Register */
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#define LTQ_PADC_DCC 0x8C
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/* Pad Control Availability Register */
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#define LTQ_PADC_AVAIL 0xF0
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#define pad_r32(p, reg) ltq_r32(p + reg)
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#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
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#define pad_w32_mask(c, clear, set, reg) \
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pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
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#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
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#define PORTS 5
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#define PINS 32
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#define PORT(x) (x / PINS)
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#define PORT_PIN(x) (x % PINS)
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#define MFP_FALCON(a, f0, f1, f2, f3) \
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{ \
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.name = #a, \
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.pin = a, \
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.func = { \
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FALCON_MUX_##f0, \
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FALCON_MUX_##f1, \
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FALCON_MUX_##f2, \
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FALCON_MUX_##f3, \
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}, \
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}
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#define GRP_MUX(a, m, p) \
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{ \
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.name = a, \
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.mux = FALCON_MUX_##m, \
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.pins = p, \
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.npins = ARRAY_SIZE(p), \
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}
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enum falcon_mux {
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FALCON_MUX_GPIO = 0,
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FALCON_MUX_RST,
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FALCON_MUX_NTR,
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FALCON_MUX_PPS,
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FALCON_MUX_MDIO,
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FALCON_MUX_LED,
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FALCON_MUX_SPI,
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FALCON_MUX_ASC,
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FALCON_MUX_I2C,
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FALCON_MUX_HOSTIF,
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FALCON_MUX_SLIC,
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FALCON_MUX_JTAG,
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FALCON_MUX_PCM,
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FALCON_MUX_MII,
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FALCON_MUX_PHY,
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FALCON_MUX_NONE = 0xffff,
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};
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static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
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static int pad_count[PORTS];
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static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
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{
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int base = bank * PINS;
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int i;
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for (i = 0; i < len; i++) {
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/* strlen("ioXYZ") + 1 = 6 */
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char *name = kzalloc(6, GFP_KERNEL);
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snprintf(name, 6, "io%d", base + i);
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d[i].number = base + i;
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d[i].name = name;
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}
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pad_count[bank] = len;
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}
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static struct ltq_mfp_pin falcon_mfp[] = {
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/* pin f0 f1 f2 f3 */
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MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
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MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
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MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
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MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
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MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
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MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
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MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
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MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
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MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
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MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
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MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
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MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
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MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
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MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
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MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
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MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
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MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
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MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
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MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
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MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
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MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
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MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
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MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
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MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
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MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
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MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
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};
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static const unsigned pins_por[] = {GPIO0};
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static const unsigned pins_ntr[] = {GPIO4};
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static const unsigned pins_ntr8k[] = {GPIO5};
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static const unsigned pins_pps[] = {GPIO5};
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static const unsigned pins_hrst[] = {GPIO6};
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static const unsigned pins_mdio[] = {GPIO7, GPIO8};
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static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
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GPIO12, GPIO13, GPIO14};
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static const unsigned pins_asc0[] = {GPIO32, GPIO33};
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static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
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static const unsigned pins_spi_cs0[] = {GPIO37};
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static const unsigned pins_spi_cs1[] = {GPIO38};
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static const unsigned pins_i2c[] = {GPIO39, GPIO40};
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static const unsigned pins_jtag[] = {GPIO41};
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static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
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static const unsigned pins_pcm[] = {GPIO44, GPIO45};
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static const unsigned pins_asc1[] = {GPIO44, GPIO45};
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static struct ltq_pin_group falcon_grps[] = {
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GRP_MUX("por", RST, pins_por),
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GRP_MUX("ntr", NTR, pins_ntr),
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GRP_MUX("ntr8k", NTR, pins_ntr8k),
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GRP_MUX("pps", PPS, pins_pps),
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GRP_MUX("hrst", RST, pins_hrst),
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GRP_MUX("mdio", MDIO, pins_mdio),
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GRP_MUX("bootled", LED, pins_bled),
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GRP_MUX("asc0", ASC, pins_asc0),
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GRP_MUX("spi", SPI, pins_spi),
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GRP_MUX("spi cs0", SPI, pins_spi_cs0),
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GRP_MUX("spi cs1", SPI, pins_spi_cs1),
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GRP_MUX("i2c", I2C, pins_i2c),
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GRP_MUX("jtag", JTAG, pins_jtag),
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GRP_MUX("slic", SLIC, pins_slic),
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GRP_MUX("pcm", PCM, pins_pcm),
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GRP_MUX("asc1", ASC, pins_asc1),
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};
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static const char * const ltq_rst_grps[] = {"por", "hrst"};
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static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
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static const char * const ltq_mdio_grps[] = {"mdio"};
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static const char * const ltq_bled_grps[] = {"bootled"};
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static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
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static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
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static const char * const ltq_i2c_grps[] = {"i2c"};
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static const char * const ltq_jtag_grps[] = {"jtag"};
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static const char * const ltq_slic_grps[] = {"slic"};
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static const char * const ltq_pcm_grps[] = {"pcm"};
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static struct ltq_pmx_func falcon_funcs[] = {
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{"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
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{"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
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{"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
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{"led", ARRAY_AND_SIZE(ltq_bled_grps)},
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{"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
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{"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
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{"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
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{"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
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{"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
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{"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
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};
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/* --------- pinconf related code --------- */
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static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
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unsigned group, unsigned long *config)
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{
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return -ENOTSUPP;
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}
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static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
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unsigned group, unsigned long *configs,
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unsigned num_configs)
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{
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return -ENOTSUPP;
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}
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static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
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unsigned pin, unsigned long *config)
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{
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struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
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enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
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void __iomem *mem = info->membase[PORT(pin)];
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switch (param) {
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case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
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*config = LTQ_PINCONF_PACK(param,
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!!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
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break;
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case LTQ_PINCONF_PARAM_SLEW_RATE:
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*config = LTQ_PINCONF_PACK(param,
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!!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
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break;
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case LTQ_PINCONF_PARAM_PULL:
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if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
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*config = LTQ_PINCONF_PACK(param, 1);
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else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
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*config = LTQ_PINCONF_PACK(param, 2);
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else
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*config = LTQ_PINCONF_PACK(param, 0);
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
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unsigned pin, unsigned long *configs,
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unsigned num_configs)
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{
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enum ltq_pinconf_param param;
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int arg;
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struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
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void __iomem *mem = info->membase[PORT(pin)];
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u32 reg;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
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arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
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switch (param) {
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case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
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reg = LTQ_PADC_DCC;
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break;
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case LTQ_PINCONF_PARAM_SLEW_RATE:
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reg = LTQ_PADC_SRC;
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break;
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case LTQ_PINCONF_PARAM_PULL:
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if (arg == 1)
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reg = LTQ_PADC_PDEN;
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else
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reg = LTQ_PADC_PUEN;
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break;
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default:
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pr_err("%s: Invalid config param %04x\n",
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pinctrl_dev_get_name(pctrldev), param);
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return -ENOTSUPP;
|
||
|
|
}
|
||
|
|
|
||
|
|
pad_w32(mem, BIT(PORT_PIN(pin)), reg);
|
||
|
|
if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
|
||
|
|
return -ENOTSUPP;
|
||
|
|
} /* for each config */
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
|
||
|
|
struct seq_file *s, unsigned offset)
|
||
|
|
{
|
||
|
|
unsigned long config;
|
||
|
|
struct pin_desc *desc;
|
||
|
|
|
||
|
|
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||
|
|
int port = PORT(offset);
|
||
|
|
|
||
|
|
seq_printf(s, " (port %d) mux %d -- ", port,
|
||
|
|
pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
|
||
|
|
|
||
|
|
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
|
||
|
|
if (!falcon_pinconf_get(pctrldev, offset, &config))
|
||
|
|
seq_printf(s, "pull %d ",
|
||
|
|
(int)LTQ_PINCONF_UNPACK_ARG(config));
|
||
|
|
|
||
|
|
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
|
||
|
|
if (!falcon_pinconf_get(pctrldev, offset, &config))
|
||
|
|
seq_printf(s, "drive-current %d ",
|
||
|
|
(int)LTQ_PINCONF_UNPACK_ARG(config));
|
||
|
|
|
||
|
|
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
|
||
|
|
if (!falcon_pinconf_get(pctrldev, offset, &config))
|
||
|
|
seq_printf(s, "slew-rate %d ",
|
||
|
|
(int)LTQ_PINCONF_UNPACK_ARG(config));
|
||
|
|
|
||
|
|
desc = pin_desc_get(pctrldev, offset);
|
||
|
|
if (desc) {
|
||
|
|
if (desc->gpio_owner)
|
||
|
|
seq_printf(s, " owner: %s", desc->gpio_owner);
|
||
|
|
} else {
|
||
|
|
seq_printf(s, " not registered");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
|
||
|
|
struct seq_file *s, unsigned selector)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct pinconf_ops falcon_pinconf_ops = {
|
||
|
|
.pin_config_get = falcon_pinconf_get,
|
||
|
|
.pin_config_set = falcon_pinconf_set,
|
||
|
|
.pin_config_group_get = falcon_pinconf_group_get,
|
||
|
|
.pin_config_group_set = falcon_pinconf_group_set,
|
||
|
|
.pin_config_dbg_show = falcon_pinconf_dbg_show,
|
||
|
|
.pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct pinctrl_desc falcon_pctrl_desc = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.pins = falcon_pads,
|
||
|
|
.confops = &falcon_pinconf_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
|
||
|
|
int mfp, int mux)
|
||
|
|
{
|
||
|
|
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||
|
|
int port = PORT(info->mfp[mfp].pin);
|
||
|
|
|
||
|
|
if ((port >= PORTS) || (!info->membase[port]))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
pad_w32(info->membase[port], mux,
|
||
|
|
LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct ltq_cfg_param falcon_cfg_params[] = {
|
||
|
|
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
|
||
|
|
{"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
|
||
|
|
{"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct ltq_pinmux_info falcon_info = {
|
||
|
|
.desc = &falcon_pctrl_desc,
|
||
|
|
.apply_mux = falcon_mux_apply,
|
||
|
|
.params = falcon_cfg_params,
|
||
|
|
.num_params = ARRAY_SIZE(falcon_cfg_params),
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/* --------- register the pinctrl layer --------- */
|
||
|
|
|
||
|
|
int pinctrl_falcon_get_range_size(int id)
|
||
|
|
{
|
||
|
|
u32 avail;
|
||
|
|
|
||
|
|
if ((id >= PORTS) || (!falcon_info.membase[id]))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
|
||
|
|
|
||
|
|
return fls(avail);
|
||
|
|
}
|
||
|
|
|
||
|
|
void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
|
||
|
|
{
|
||
|
|
pinctrl_add_gpio_range(falcon_info.pctrl, range);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int pinctrl_falcon_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device_node *np;
|
||
|
|
int pad_count = 0;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
/* load and remap the pad resources of the different banks */
|
||
|
|
for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
|
||
|
|
struct platform_device *ppdev = of_find_device_by_node(np);
|
||
|
|
const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
|
||
|
|
struct resource res;
|
||
|
|
u32 avail;
|
||
|
|
int pins;
|
||
|
|
|
||
|
|
if (!of_device_is_available(np))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (!ppdev) {
|
||
|
|
dev_err(&pdev->dev, "failed to find pad pdev\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
if (!bank || *bank >= PORTS)
|
||
|
|
continue;
|
||
|
|
if (of_address_to_resource(np, 0, &res))
|
||
|
|
continue;
|
||
|
|
falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
|
||
|
|
if (IS_ERR(falcon_info.clk[*bank])) {
|
||
|
|
dev_err(&ppdev->dev, "failed to get clock\n");
|
||
|
|
return PTR_ERR(falcon_info.clk[*bank]);
|
||
|
|
}
|
||
|
|
falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
|
||
|
|
&res);
|
||
|
|
if (IS_ERR(falcon_info.membase[*bank]))
|
||
|
|
return PTR_ERR(falcon_info.membase[*bank]);
|
||
|
|
|
||
|
|
avail = pad_r32(falcon_info.membase[*bank],
|
||
|
|
LTQ_PADC_AVAIL);
|
||
|
|
pins = fls(avail);
|
||
|
|
lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
|
||
|
|
pad_count += pins;
|
||
|
|
clk_enable(falcon_info.clk[*bank]);
|
||
|
|
dev_dbg(&pdev->dev, "found %s with %d pads\n",
|
||
|
|
res.name, pins);
|
||
|
|
}
|
||
|
|
dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
|
||
|
|
falcon_pctrl_desc.name = dev_name(&pdev->dev);
|
||
|
|
falcon_pctrl_desc.npins = pad_count;
|
||
|
|
|
||
|
|
falcon_info.mfp = falcon_mfp;
|
||
|
|
falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
|
||
|
|
falcon_info.grps = falcon_grps;
|
||
|
|
falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
|
||
|
|
falcon_info.funcs = falcon_funcs;
|
||
|
|
falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
|
||
|
|
|
||
|
|
ret = ltq_pinctrl_register(pdev, &falcon_info);
|
||
|
|
if (!ret)
|
||
|
|
dev_info(&pdev->dev, "Init done\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id falcon_match[] = {
|
||
|
|
{ .compatible = "lantiq,pinctrl-falcon" },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, falcon_match);
|
||
|
|
|
||
|
|
static struct platform_driver pinctrl_falcon_driver = {
|
||
|
|
.probe = pinctrl_falcon_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "pinctrl-falcon",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = falcon_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
int __init pinctrl_falcon_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&pinctrl_falcon_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
core_initcall_sync(pinctrl_falcon_init);
|