505 lines
15 KiB
Text
505 lines
15 KiB
Text
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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qcom,msm-cam@1b00000 {
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compatible = "qcom,msm-cam";
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reg = <0x8c0000 0x40000>;
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reg-names = "msm-cam";
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status = "ok";
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bus-vectors = "suspend", "svs", "nominal", "turbo";
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qcom,bus-votes = <0 320000000 640000000 640000000>;
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};
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qcom,csiphy@1b0ac00 {
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status = "ok";
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cell-index = <0>;
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compatible = "qcom,csiphy-v3.1", "qcom,csiphy";
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reg = <0x1b0ac00 0x200>,
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<0x1b00030 0x4>;
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reg-names = "csiphy", "csiphy_clk_mux";
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interrupts = <0 78 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_csi0phytimer_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0phytimer_clk>,
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<&clock_gcc clk_camss_top_ahb_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0phy_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ahb_src", "csi_phy_clk",
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"camss_ahb_clk";
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qcom,clock-rates = <0 61540000 160000000 0 0 0 0>;
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};
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qcom,csiphy@1b0b000 {
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status = "ok";
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cell-index = <1>;
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compatible = "qcom,csiphy-v3.1", "qcom,csiphy";
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reg = <0x1b0b000 0x200>,
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<0x1b00038 0x4>;
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reg-names = "csiphy", "csiphy_clk_mux";
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interrupts = <0 79 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_csi1phytimer_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1phytimer_clk>,
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<&clock_gcc clk_camss_top_ahb_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1phy_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ahb_src", "csi_phy_clk",
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"camss_ahb_clk";
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qcom,clock-rates = <0 61540000 160000000 0 0 0 0>;
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};
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qcom,csid@1b08000 {
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status = "ok";
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cell-index = <0>;
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compatible = "qcom,csid-v3.4.1", "qcom,csid";
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reg = <0x1b08000 0x100>;
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reg-names = "csid";
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interrupts = <0 51 0>;
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interrupt-names = "csid";
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qcom,csi-vdd-voltage = <1200000>;
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qcom,mipi-csi-vdd-supply = <&pm8950_l2>;
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi0_ahb_clk>,
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<&clock_gcc clk_csi0_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0_clk>,
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<&clock_gcc clk_gcc_camss_csi0pix_clk>,
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<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk",
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"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
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"csi_clk", "csi_pix_clk",
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"csi_rdi_clk", "camss_ahb_clk";
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qcom,clock-rates = <0 61540000 0 160000000 0 0 0 0>;
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};
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qcom,csid@1b08400 {
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status = "ok";
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cell-index = <1>;
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compatible = "qcom,csid-v3.4.1", "qcom,csid";
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reg = <0x1b08400 0x100>;
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reg-names = "csid";
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interrupts = <0 52 0>;
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interrupt-names = "csid";
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qcom,csi-vdd-voltage = <1200000>;
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qcom,mipi-csi-vdd-supply = <&pm8950_l2>;
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi1_ahb_clk>,
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<&clock_gcc clk_csi1_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1_clk>,
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<&clock_gcc clk_gcc_camss_csi1pix_clk>,
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<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk",
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"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
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"csi_clk", "csi_pix_clk",
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"csi_rdi_clk", "camss_ahb_clk";
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qcom,clock-rates = <0 61540000 0 160000000 0 0 0 0>;
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};
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qcom,csid@1b08800 {
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status = "ok";
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cell-index = <2>;
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compatible = "qcom,csid-v3.4.1", "qcom,csid";
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reg = <0x1b08800 0x100>;
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reg-names = "csid";
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interrupts = <0 153 0>;
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interrupt-names = "csid";
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qcom,csi-vdd-voltage = <1200000>;
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qcom,mipi-csi-vdd-supply = <&pm8950_l2>;
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi2_ahb_clk>,
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<&clock_gcc clk_csi2_clk_src>,
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<&clock_gcc clk_gcc_camss_csi2_clk>,
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<&clock_gcc clk_gcc_camss_csi2pix_clk>,
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<&clock_gcc clk_gcc_camss_csi2rdi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk",
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"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
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"csi_clk", "csi_pix_clk",
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"csi_rdi_clk", "camss_ahb_clk";
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qcom,clock-rates = <0 61540000 0 160000000 0 0 0 0>;
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};
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qcom,ispif@1b0a000 {
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cell-index = <0>;
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compatible = "qcom,ispif-v3.0", "qcom,ispif";
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reg = <0x1b0a000 0x500>,
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<0x1b00020 0x10>;
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reg-names = "ispif", "csi_clk_mux";
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interrupts = <0 55 0>;
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interrupt-names = "ispif";
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qcom,num-isps = <0x2>;
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vfe0_vdd_supply = <&gdsc_vfe>;
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vfe1_vdd_supply = <&gdsc_vfe1>;
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clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_csi0_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0_clk>,
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<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
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<&clock_gcc clk_gcc_camss_csi0pix_clk>,
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<&clock_gcc clk_csi1_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1_clk>,
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<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
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<&clock_gcc clk_gcc_camss_csi1pix_clk>,
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<&clock_gcc clk_csi2_clk_src>,
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<&clock_gcc clk_gcc_camss_csi2_clk>,
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<&clock_gcc clk_gcc_camss_csi2rdi_clk>,
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<&clock_gcc clk_gcc_camss_csi2pix_clk>,
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<&clock_gcc clk_vfe0_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe0_clk>,
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<&clock_gcc clk_vfe1_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe1_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;
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clock-names = "ispif_ahb_clk",
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"csi0_src_clk", "csi0_clk",
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"csi0_rdi_clk", "csi0_pix_clk",
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"csi1_src_clk", "csi1_clk",
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"csi1_rdi_clk", "csi1_pix_clk",
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"csi2_src_clk", "csi2_clk",
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"csi2_rdi_clk", "csi2_pix_clk",
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"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
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"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
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qcom,clock-rates = <61540000
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200000000 0 0 0
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200000000 0 0 0
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200000000 0 0 0
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0 0 0
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0 0 0>;
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qcom,clock-control = "SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
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};
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qcom,vfe {
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compatible = "qcom,vfe";
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ranges;
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vfe0: qcom,vfe0@1b10000 {
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cell-index = <0>;
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compatible = "qcom,vfe40";
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reg = <0x1b10000 0x1000>,
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<0x1b40000 0x200>;
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reg-names = "vfe", "vfe_vbif";
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interrupts = <0 57 0>;
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interrupt-names = "vfe";
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vdd-supply = <&gdsc_vfe>;
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>,
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<&clock_gcc clk_vfe0_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_vfe_ahb_clk>,
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<&clock_gcc clk_gcc_camss_vfe_axi_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;
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clock-names = "camss_top_ahb_clk", "camss_ahb_clk",
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"vfe_clk_src", "camss_vfe_vfe_clk",
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"camss_csi_vfe_clk", "iface_clk",
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"bus_clk", "iface_ahb_clk";
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qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
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qos-entries = <8>;
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qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8
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0x2DC 0x2E0>;
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qos-settings = <0xA555A555
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0xA555A555 0xA555A555
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0xA555A555 0xA555A555
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0xA555A555 0xA555A555
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0x0001A555>;
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vbif-entries = <1>;
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vbif-regs = <0x124>;
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vbif-settings = <0x3>;
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ds-entries = <17>;
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ds-regs = <0x988 0x98C 0x990 0x994 0x998
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0x99C 0x9A0 0x9A4 0x9A8 0x9AC 0x9B0
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0x9B4 0x9B8 0x9BC 0x9C0 0x9C4 0x9C8>;
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ds-settings = <0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0x00000103>;
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max-clk-nominal = <308570000>;
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max-clk-turbo = <360000000>;
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};
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vfe1: qcom,vfe1@1b14000 {
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cell-index = <1>;
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compatible = "qcom,vfe40";
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reg = <0x1b14000 0x1000>,
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<0x1ba0000 0x200>;
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reg-names = "vfe", "vfe_vbif";
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interrupts = <0 29 0>;
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interrupt-names = "vfe";
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vdd-supply = <&gdsc_vfe1>;
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>,
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<&clock_gcc clk_vfe1_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe1_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe1_clk>,
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<&clock_gcc clk_gcc_camss_vfe1_ahb_clk>,
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<&clock_gcc clk_gcc_camss_vfe1_axi_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>;
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clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",
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"vfe_clk_src", "camss_vfe_vfe_clk",
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"camss_csi_vfe_clk", "iface_clk",
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"bus_clk", "iface_ahb_clk";
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qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
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qos-entries = <8>;
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qos-regs = <0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8
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0x2DC 0x2E0>;
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qos-settings = <0xA555A555
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0xA555A555 0xA555A555
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0xA555A555 0xA555A555
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0xA555A555 0xA555A555
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0x0001A555>;
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vbif-entries = <1>;
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vbif-regs = <0x124>;
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vbif-settings = <0x3>;
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ds-entries = <17>;
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ds-regs = <0x988 0x98C 0x990 0x994 0x998
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0x99C 0x9A0 0x9A4 0x9A8 0x9AC 0x9B0
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0x9B4 0x9B8 0x9BC 0x9C0 0x9C4 0x9C8>;
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ds-settings = <0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111
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|
|
0xCCCC1111 0xCCCC1111
|
||
|
|
0xCCCC1111 0xCCCC1111
|
||
|
|
0xCCCC1111 0xCCCC1111
|
||
|
|
0xCCCC1111 0xCCCC1111
|
||
|
|
0xCCCC1111 0x00000103>;
|
||
|
|
max-clk-nominal = <308570000>;
|
||
|
|
max-clk-turbo = <360000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
qcom,cam_smmu {
|
||
|
|
status = "ok";
|
||
|
|
compatible = "qcom,msm-cam-smmu";
|
||
|
|
msm_cam_smmu_cb1: msm_cam_smmu_cb1 {
|
||
|
|
compatible = "qcom,qsmmu-cam-cb";
|
||
|
|
iommus = <&apps_iommu 0x400>,
|
||
|
|
<&apps_iommu 0x3000>;
|
||
|
|
label = "vfe";
|
||
|
|
qcom,scratch-buf-support;
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_cb2: msm_cam_smmu_cb2 {
|
||
|
|
compatible = "qcom,qsmmu-cam-cb";
|
||
|
|
label = "vfe_secure";
|
||
|
|
qcom,secure-context;
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
|
||
|
|
compatible = "qcom,qsmmu-cam-cb";
|
||
|
|
iommus = <&apps_iommu 0x2400>;
|
||
|
|
label = "cpp";
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
|
||
|
|
compatible = "qcom,qsmmu-cam-cb";
|
||
|
|
iommus = <&apps_iommu 0x2000>;
|
||
|
|
label = "jpeg_enc0";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,jpeg@1b1c000 {
|
||
|
|
status = "ok";
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,jpeg";
|
||
|
|
reg = <0x1b1c000 0x400>,
|
||
|
|
<0x1b60000 0xc30>;
|
||
|
|
reg-names = "jpeg";
|
||
|
|
interrupts = <0 59 0>;
|
||
|
|
interrupt-names = "jpeg";
|
||
|
|
vdd-supply = <&gdsc_jpeg>;
|
||
|
|
clock-names = "core_clk", "iface_clk", "bus_clk0",
|
||
|
|
"camss_top_ahb_clk", "camss_ahb_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_jpeg_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_jpeg_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_top_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_ahb_clk>;
|
||
|
|
qcom,clock-rates = <266670000 0 0 0 0>;
|
||
|
|
qos-reg-settings = <0x28 0x0000550E>,
|
||
|
|
<0xC8 0x00005555>;
|
||
|
|
vbif-reg-settings = <0xC0 0x10101000>,
|
||
|
|
<0xB0 0x10100010>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,irqrouter@1b00000 {
|
||
|
|
status = "ok";
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,irqrouter";
|
||
|
|
reg = <0x1b00000 0x100>;
|
||
|
|
reg-names = "irqrouter";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cpp@1b04000 {
|
||
|
|
status = "ok";
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cpp";
|
||
|
|
reg = <0x1b04000 0x100>,
|
||
|
|
<0x1b80000 0x200>,
|
||
|
|
<0x1b18000 0x018>;
|
||
|
|
reg-names = "cpp", "cpp_vbif", "cpp_hw";
|
||
|
|
interrupts = <0 49 0>;
|
||
|
|
interrupt-names = "cpp";
|
||
|
|
vdd-supply = <&gdsc_cpp>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
|
||
|
|
<&clock_gcc clk_cpp_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cpp_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cpp_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cpp_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_micro_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_ahb_clk>;
|
||
|
|
clock-names = "camss_top_ahb_clk", "cpp_core_clk",
|
||
|
|
"camss_vfe_cpp_ahb_clk", "camss_vfe_cpp_axi_clk",
|
||
|
|
"camss_vfe_cpp_clk","micro_iface_clk", "camss_ahb_clk";
|
||
|
|
qcom,clock-rates = <0 180000000 0 0 180000000 0 0>;
|
||
|
|
qcom,min-clock-rate = <133330000>;
|
||
|
|
bus_master = <1>;
|
||
|
|
qcom,cpp-fw-payload-info {
|
||
|
|
qcom,stripe-base = <156>;
|
||
|
|
qcom,plane-base = <141>;
|
||
|
|
qcom,stripe-size = <27>;
|
||
|
|
qcom,plane-size = <5>;
|
||
|
|
qcom,fe-ptr-off = <5>;
|
||
|
|
qcom,we-ptr-off = <11>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
cci: qcom,cci@1b0c000 {
|
||
|
|
status = "ok";
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cci";
|
||
|
|
reg = <0x1b0c000 0x1000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "cci";
|
||
|
|
interrupts = <0 50 0>;
|
||
|
|
interrupt-names = "cci";
|
||
|
|
clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
|
||
|
|
<&clock_gcc clk_cci_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cci_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cci_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_top_ahb_clk>;
|
||
|
|
clock-names = "ispif_ahb_clk", "cci_src_clk",
|
||
|
|
"cci_ahb_clk", "camss_cci_clk",
|
||
|
|
"camss_ahb_clk", "camss_top_ahb_clk";
|
||
|
|
qcom,clock-rates = <61540000 19200000 0 0 0 0>,
|
||
|
|
<61540000 37500000 0 0 0 0>;
|
||
|
|
pinctrl-names = "cci_default", "cci_suspend";
|
||
|
|
pinctrl-0 = <&cci0_active &cci1_active>;
|
||
|
|
pinctrl-1 = <&cci0_suspend &cci1_suspend>;
|
||
|
|
gpios = <&msm_gpio 29 0>,
|
||
|
|
<&msm_gpio 30 0>,
|
||
|
|
<&msm_gpio 31 0>,
|
||
|
|
<&msm_gpio 32 0>;
|
||
|
|
qcom,gpio-tbl-num = <0 1 2 3>;
|
||
|
|
qcom,gpio-tbl-flags = <1 1 1 1>;
|
||
|
|
qcom,gpio-tbl-label = "CCI_I2C_DATA0",
|
||
|
|
"CCI_I2C_CLK0",
|
||
|
|
"CCI_I2C_DATA1",
|
||
|
|
"CCI_I2C_CLK1";
|
||
|
|
i2c_freq_100Khz: qcom,i2c_standard_mode {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
i2c_freq_400Khz: qcom,i2c_fast_mode {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
i2c_freq_custom: qcom,i2c_custom_mode {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c_freq_100Khz {
|
||
|
|
qcom,hw-thigh = <78>;
|
||
|
|
qcom,hw-tlow = <114>;
|
||
|
|
qcom,hw-tsu-sto = <28>;
|
||
|
|
qcom,hw-tsu-sta = <28>;
|
||
|
|
qcom,hw-thd-dat = <10>;
|
||
|
|
qcom,hw-thd-sta = <77>;
|
||
|
|
qcom,hw-tbuf = <118>;
|
||
|
|
qcom,hw-scl-stretch-en = <0>;
|
||
|
|
qcom,hw-trdhld = <6>;
|
||
|
|
qcom,hw-tsp = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c_freq_400Khz {
|
||
|
|
qcom,hw-thigh = <20>;
|
||
|
|
qcom,hw-tlow = <28>;
|
||
|
|
qcom,hw-tsu-sto = <21>;
|
||
|
|
qcom,hw-tsu-sta = <21>;
|
||
|
|
qcom,hw-thd-dat = <13>;
|
||
|
|
qcom,hw-thd-sta = <18>;
|
||
|
|
qcom,hw-tbuf = <32>;
|
||
|
|
qcom,hw-scl-stretch-en = <0>;
|
||
|
|
qcom,hw-trdhld = <6>;
|
||
|
|
qcom,hw-tsp = <3>;
|
||
|
|
status = "ok";
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c_freq_custom {
|
||
|
|
qcom,hw-thigh = <15>;
|
||
|
|
qcom,hw-tlow = <28>;
|
||
|
|
qcom,hw-tsu-sto = <21>;
|
||
|
|
qcom,hw-tsu-sta = <21>;
|
||
|
|
qcom,hw-thd-dat = <13>;
|
||
|
|
qcom,hw-thd-sta = <18>;
|
||
|
|
qcom,hw-tbuf = <25>;
|
||
|
|
qcom,hw-scl-stretch-en = <1>;
|
||
|
|
qcom,hw-trdhld = <6>;
|
||
|
|
qcom,hw-tsp = <3>;
|
||
|
|
status = "ok";
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c_freq_1Mhz {
|
||
|
|
qcom,hw-thigh = <16>;
|
||
|
|
qcom,hw-tlow = <22>;
|
||
|
|
qcom,hw-tsu-sto = <17>;
|
||
|
|
qcom,hw-tsu-sta = <18>;
|
||
|
|
qcom,hw-thd-dat = <16>;
|
||
|
|
qcom,hw-thd-sta = <15>;
|
||
|
|
qcom,hw-tbuf = <19>;
|
||
|
|
qcom,hw-scl-stretch-en = <1>;
|
||
|
|
qcom,hw-trdhld = <3>;
|
||
|
|
qcom,hw-tsp = <3>;
|
||
|
|
qcom,cci-clk-src = <37500000>;
|
||
|
|
status = "ok";
|
||
|
|
};
|