203 lines
8 KiB
C
203 lines
8 KiB
C
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/*
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* max77843-muic-hv.h - MUIC for the Maxim 77843
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*
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* Copyright (C) 2011 Samsung Electrnoics
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* Seoyoung Jeong <seo0.jeong@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on max77843-muic.h
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*
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*/
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#ifndef __MAX77843_MUIC_HV_H__
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#define __MAX77843_MUIC_HV_H__
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#define MUIC_HV_DEV_NAME "muic-max77843-hv"
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/* MAX77828 INTMASK3 register */
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#define INTMASK3_VBADCM_SHIFT 0
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#define INTMASK3_VDNMONM_SHIFT 1
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#define INTMASK3_DNRESM_SHIFT 2
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#define INTMASK3_MPNACKM_SHIFT 3
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#define INTMASK3_MRXBUFOWM_SHIFT 4
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#define INTMASK3_MRXTRFM_SHIFT 5
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#define INTMASK3_MRXPERRM_SHIFT 6
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#define INTMASK3_MRXRDYM_SHIFT 7
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#define INTMASK3_VBADCM_MASK (MAX77843_ENABLE_BIT << INTMASK3_VBADCM_SHIFT)
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#define INTMASK3_VDNMONM_MASK (MAX77843_ENABLE_BIT << INTMASK3_VDNMONM_SHIFT)
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#define INTMASK3_DNRESM_MASK (MAX77843_ENABLE_BIT << INTMASK3_DNRESM_SHIFT)
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#define INTMASK3_MPNACKM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MPNACKM_SHIFT)
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#define INTMASK3_MRXBUFOWM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXBUFOWM_SHIFT)
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#define INTMASK3_MRXTRFM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXTRFM_SHIFT)
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#define INTMASK3_MRXPERRM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXPERRM_SHIFT)
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#define INTMASK3_MRXRDYM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXRDYM_SHIFT)
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/* MAX77843 HVCONTROL1 register */
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#define HVCONTROL1_DPDNVDEN_SHIFT 0
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#define HVCONTROL1_DNVD_SHIFT 1
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#define HVCONTROL1_DPVD_SHIFT 3
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#define HVCONTROL1_VBUSADCEN_SHIFT 5
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#define HVCONTROL1_DPDNVDEN_MASK (0x1 << HVCONTROL1_DPDNVDEN_SHIFT)
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#define HVCONTROL1_DNVD_MASK (0x3 << HVCONTROL1_DNVD_SHIFT)
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#define HVCONTROL1_DPVD_MASK (0x3 << HVCONTROL1_DPVD_SHIFT)
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#define HVCONTROL1_VBUSADCEN_MASK (0x1 << HVCONTROL1_VBUSADCEN_SHIFT)
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/* MAX77843 STATUS3 register */
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#define STATUS3_VBADC_SHIFT 0
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#define STATUS3_VDNMON_SHIFT 4
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#define STATUS3_DNRES_SHIFT 5
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#define STATUS3_MPNACK_SHIFT 6
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#define STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT)
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#define STATUS3_VDNMON_MASK (0x1 << STATUS3_VDNMON_SHIFT)
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#define STATUS3_DNRES_MASK (0x1 << STATUS3_DNRES_SHIFT)
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#define STATUS3_MPNACK_MASK (0x1 << STATUS3_MPNACK_SHIFT)
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/* MAX77843 HVCONTROL2 register */
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#define HVCONTROL2_HVDIGEN_SHIFT 0
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#define HVCONTROL2_DP06EN_SHIFT 1
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#define HVCONTROL2_DNRESEN_SHIFT 2
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#define HVCONTROL2_MPING_SHIFT 3
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#define HVCONTROL2_MTXEN_SHIFT 4
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#define HVCONTROL2_MTXBUSRES_SHIFT 5
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#define HVCONTROL2_MPNGENB_SHIFT 6
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#define HVCONTROL2_HVDIGEN_MASK (0x1 << HVCONTROL2_HVDIGEN_SHIFT)
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#define HVCONTROL2_DP06EN_MASK (0x1 << HVCONTROL2_DP06EN_SHIFT)
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#define HVCONTROL2_DNRESEN_MASK (0x1 << HVCONTROL2_DNRESEN_SHIFT)
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#define HVCONTROL2_MPING_MASK (0x1 << HVCONTROL2_MPING_SHIFT)
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#define HVCONTROL2_MTXEN_MASK (0x1 << HVCONTROL2_MTXEN_SHIFT)
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#define HVCONTROL2_MTXBUSRES_MASK (0x1 << HVCONTROL2_MTXBUSRES_SHIFT)
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#define HVCONTROL2_MPNGENB_MASK (0x1 << HVCONTROL2_MPNGENB_SHIFT)
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/* MAX77843 HVRXBYTE register */
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#define HVRXBYTE_MAX 16
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/* MAX77843 AFC charger W/A Check NUM */
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#define AFC_CHARGER_WA_PING 3
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/* MAX77843 MPing miss SW Workaround - delay time */
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#define MPING_MISS_WA_TIME 2000
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typedef enum {
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DPDNVDEN_DISABLE = 0x00,
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DPDNVDEN_ENABLE = (0x1 << HVCONTROL1_DPDNVDEN_SHIFT),
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DPDNVDEN_DONTCARE = 0xff,
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} dpdnvden_t;
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typedef enum {
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VDNMON_LOW = 0x00,
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VDNMON_HIGH = (0x1 << STATUS3_VDNMON_SHIFT),
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VDNMON_DONTCARE = 0xff,
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} vdnmon_t;
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typedef enum {
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VBADC_VBDET = 0x00,
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VBADC_4V_5V = (0x1 << STATUS3_VBADC_SHIFT),
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VBADC_5V_6V = (0x2 << STATUS3_VBADC_SHIFT),
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VBADC_6V_7V = (0x3 << STATUS3_VBADC_SHIFT),
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VBADC_7V_8V = (0x4 << STATUS3_VBADC_SHIFT),
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VBADC_8V_9V = (0x5 << STATUS3_VBADC_SHIFT),
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VBADC_9V_10V = (0x6 << STATUS3_VBADC_SHIFT),
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VBADC_10V_12V = (0x7 << STATUS3_VBADC_SHIFT),
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VBADC_12V_13V = (0x8 << STATUS3_VBADC_SHIFT),
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VBADC_13V_14V = (0x9 << STATUS3_VBADC_SHIFT),
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VBADC_14V_15V = (0xA << STATUS3_VBADC_SHIFT),
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VBADC_15V_16V = (0xB << STATUS3_VBADC_SHIFT),
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VBADC_16V_17V = (0xC << STATUS3_VBADC_SHIFT),
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VBADC_17V_18V = (0xD << STATUS3_VBADC_SHIFT),
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VBADC_18V_19V = (0xE << STATUS3_VBADC_SHIFT),
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VBADC_19V = (0xF << STATUS3_VBADC_SHIFT),
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VBADC_QC_5V = 0xeb,
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VBADC_QC_9V = 0xec,
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VBADC_QC_12V = 0xed,
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VBADC_QC_20V = 0xee,
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VBADC_AFC_5V = 0xfa,
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VBADC_AFC_9V = 0xfb,
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VBADC_AFC_ERR_V = 0xfc,
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VBADC_AFC_ERR_V_NOT_0 = 0xfd,
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VBADC_ANY = 0xfe,
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VBADC_DONTCARE = 0xff,
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} vbadc_t;
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enum {
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HV_SUPPORT_QC_5V = 5,
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HV_SUPPORT_QC_9V = 9,
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HV_SUPPORT_QC_12V = 12,
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HV_SUPPORT_QC_20V = 20,
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};
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enum max77843_reg_hv_val {
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MAX77843_MUIC_HVCONTROL1_DPVD_06 = (0x2 << HVCONTROL1_DPVD_SHIFT),
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MAX77843_MUIC_HVCONTROL1_11 = (MAX77843_MUIC_HVCONTROL1_DPVD_06 | \
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HVCONTROL1_DPDNVDEN_MASK),
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MAX77843_MUIC_HVCONTROL1_31 = (HVCONTROL1_VBUSADCEN_MASK | \
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MAX77843_MUIC_HVCONTROL1_DPVD_06 | \
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HVCONTROL1_DPDNVDEN_MASK),
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MAX77843_MUIC_HVCONTROL2_06 = (HVCONTROL2_DP06EN_MASK | HVCONTROL2_DNRESEN_MASK),
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MAX77843_MUIC_HVCONTROL2_13 = (HVCONTROL2_MTXEN_MASK | HVCONTROL2_DP06EN_MASK | \
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HVCONTROL2_HVDIGEN_MASK),
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MAX77843_MUIC_HVCONTROL2_1B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
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HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
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MAX77843_MUIC_HVCONTROL2_1F = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
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HVCONTROL2_DNRESEN_MASK | HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
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MAX77843_MUIC_HVCONTROL2_5B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
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HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK | HVCONTROL2_MPNGENB_MASK),
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MAX77843_MUIC_INTMASK3_FB = (INTMASK3_MRXRDYM_MASK | INTMASK3_MRXPERRM_MASK | \
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INTMASK3_MRXTRFM_MASK | INTMASK3_MRXBUFOWM_MASK | \
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INTMASK3_MPNACKM_MASK | INTMASK3_VDNMONM_MASK | \
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INTMASK3_VBADCM_MASK),
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};
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extern bool muic_check_dev_ta(struct max77843_muic_data *muic_data);
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extern bool muic_check_is_hv_dev(struct max77843_muic_data *muic_data);
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extern muic_attached_dev_t hv_muic_check_id_err
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(struct max77843_muic_data *muic_data, muic_attached_dev_t new_dev);
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extern void max77843_hv_muic_reset_hvcontrol_reg(struct max77843_muic_data *muic_data);
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#if defined(CONFIG_OF)
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extern int of_max77843_hv_muic_dt(struct max77843_muic_data *muic_data);
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#endif
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extern int max77843_afc_muic_irq_init(struct max77843_muic_data *muic_data);
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extern void max77843_hv_muic_free_irqs(struct max77843_muic_data *muic_data);
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extern int max77843_muic_hv_update_reg(struct i2c_client *i2c,
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const u8 reg, const u8 val, const u8 mask, const bool debug_en);
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extern void max77843_muic_set_afc_ready(struct max77843_muic_data *muic_data, bool value);
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extern void max77843_hv_muic_init_check_dpdnvden (struct max77843_muic_data *muic_data);
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extern void max77843_hv_muic_init_detect(struct max77843_muic_data *muic_data);
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extern void max77843_hv_muic_initialize(struct max77843_muic_data *muic_data);
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extern void max77843_hv_muic_remove(struct max77843_muic_data *muic_data);
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extern void max77843_hv_muic_remove_wo_free_irq(struct max77843_muic_data *muic_data);
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extern void max77843_muic_set_adcmode_always(struct max77843_muic_data *muic_data);
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#if !defined(CONFIG_SEC_FACTORY)
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extern void max77843_muic_set_adcmode_oneshot(struct max77843_muic_data *muic_data);
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#endif /* !CONFIG_SEC_FACTORY */
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extern void max77843_hv_muic_adcmode_oneshot(struct max77843_muic_data *muic_data);
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extern void max77843_muic_prepare_afc_charger(struct max77843_muic_data *muic_data);
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extern bool max77843_muic_check_change_dev_afc_charger
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(struct max77843_muic_data *muic_data, muic_attached_dev_t new_dev);
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#endif /* __MAX77843_MUIC_HV_H__ */
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