242 lines
9.3 KiB
C
242 lines
9.3 KiB
C
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/*
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* asm-offsets.c Generate definitions needed by assembly language modules.
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* This code generates raw asm output which is post-processed
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* to extract and format the required data.
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*
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* Anthony Xu <anthony.xu@intel.com>
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* Xiantao Zhang <xiantao.zhang@intel.com>
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* Copyright (c) 2007 Intel Corporation KVM support.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/kvm_host.h>
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#include <linux/kbuild.h>
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#include "vcpu.h"
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void foo(void)
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{
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DEFINE(VMM_TASK_SIZE, sizeof(struct kvm_vcpu));
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DEFINE(VMM_PT_REGS_SIZE, sizeof(struct kvm_pt_regs));
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BLANK();
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DEFINE(VMM_VCPU_META_RR0_OFFSET,
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offsetof(struct kvm_vcpu, arch.metaphysical_rr0));
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DEFINE(VMM_VCPU_META_SAVED_RR0_OFFSET,
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offsetof(struct kvm_vcpu,
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arch.metaphysical_saved_rr0));
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DEFINE(VMM_VCPU_VRR0_OFFSET,
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offsetof(struct kvm_vcpu, arch.vrr[0]));
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DEFINE(VMM_VPD_IRR0_OFFSET,
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offsetof(struct vpd, irr[0]));
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DEFINE(VMM_VCPU_ITC_CHECK_OFFSET,
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offsetof(struct kvm_vcpu, arch.itc_check));
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DEFINE(VMM_VCPU_IRQ_CHECK_OFFSET,
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offsetof(struct kvm_vcpu, arch.irq_check));
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DEFINE(VMM_VPD_VHPI_OFFSET,
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offsetof(struct vpd, vhpi));
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DEFINE(VMM_VCPU_VSA_BASE_OFFSET,
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offsetof(struct kvm_vcpu, arch.vsa_base));
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DEFINE(VMM_VCPU_VPD_OFFSET,
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offsetof(struct kvm_vcpu, arch.vpd));
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DEFINE(VMM_VCPU_IRQ_CHECK,
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offsetof(struct kvm_vcpu, arch.irq_check));
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DEFINE(VMM_VCPU_TIMER_PENDING,
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offsetof(struct kvm_vcpu, arch.timer_pending));
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DEFINE(VMM_VCPU_META_SAVED_RR0_OFFSET,
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offsetof(struct kvm_vcpu, arch.metaphysical_saved_rr0));
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DEFINE(VMM_VCPU_MODE_FLAGS_OFFSET,
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offsetof(struct kvm_vcpu, arch.mode_flags));
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DEFINE(VMM_VCPU_ITC_OFS_OFFSET,
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offsetof(struct kvm_vcpu, arch.itc_offset));
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DEFINE(VMM_VCPU_LAST_ITC_OFFSET,
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offsetof(struct kvm_vcpu, arch.last_itc));
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DEFINE(VMM_VCPU_SAVED_GP_OFFSET,
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offsetof(struct kvm_vcpu, arch.saved_gp));
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BLANK();
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DEFINE(VMM_PT_REGS_B6_OFFSET,
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offsetof(struct kvm_pt_regs, b6));
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DEFINE(VMM_PT_REGS_B7_OFFSET,
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offsetof(struct kvm_pt_regs, b7));
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DEFINE(VMM_PT_REGS_AR_CSD_OFFSET,
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offsetof(struct kvm_pt_regs, ar_csd));
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DEFINE(VMM_PT_REGS_AR_SSD_OFFSET,
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offsetof(struct kvm_pt_regs, ar_ssd));
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DEFINE(VMM_PT_REGS_R8_OFFSET,
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offsetof(struct kvm_pt_regs, r8));
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DEFINE(VMM_PT_REGS_R9_OFFSET,
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offsetof(struct kvm_pt_regs, r9));
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DEFINE(VMM_PT_REGS_R10_OFFSET,
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offsetof(struct kvm_pt_regs, r10));
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DEFINE(VMM_PT_REGS_R11_OFFSET,
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offsetof(struct kvm_pt_regs, r11));
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DEFINE(VMM_PT_REGS_CR_IPSR_OFFSET,
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offsetof(struct kvm_pt_regs, cr_ipsr));
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DEFINE(VMM_PT_REGS_CR_IIP_OFFSET,
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offsetof(struct kvm_pt_regs, cr_iip));
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DEFINE(VMM_PT_REGS_CR_IFS_OFFSET,
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offsetof(struct kvm_pt_regs, cr_ifs));
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DEFINE(VMM_PT_REGS_AR_UNAT_OFFSET,
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offsetof(struct kvm_pt_regs, ar_unat));
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DEFINE(VMM_PT_REGS_AR_PFS_OFFSET,
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offsetof(struct kvm_pt_regs, ar_pfs));
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DEFINE(VMM_PT_REGS_AR_RSC_OFFSET,
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offsetof(struct kvm_pt_regs, ar_rsc));
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DEFINE(VMM_PT_REGS_AR_RNAT_OFFSET,
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offsetof(struct kvm_pt_regs, ar_rnat));
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DEFINE(VMM_PT_REGS_AR_BSPSTORE_OFFSET,
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offsetof(struct kvm_pt_regs, ar_bspstore));
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DEFINE(VMM_PT_REGS_PR_OFFSET,
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offsetof(struct kvm_pt_regs, pr));
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DEFINE(VMM_PT_REGS_B0_OFFSET,
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offsetof(struct kvm_pt_regs, b0));
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DEFINE(VMM_PT_REGS_LOADRS_OFFSET,
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offsetof(struct kvm_pt_regs, loadrs));
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DEFINE(VMM_PT_REGS_R1_OFFSET,
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offsetof(struct kvm_pt_regs, r1));
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DEFINE(VMM_PT_REGS_R12_OFFSET,
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offsetof(struct kvm_pt_regs, r12));
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DEFINE(VMM_PT_REGS_R13_OFFSET,
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offsetof(struct kvm_pt_regs, r13));
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DEFINE(VMM_PT_REGS_AR_FPSR_OFFSET,
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offsetof(struct kvm_pt_regs, ar_fpsr));
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DEFINE(VMM_PT_REGS_R15_OFFSET,
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offsetof(struct kvm_pt_regs, r15));
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DEFINE(VMM_PT_REGS_R14_OFFSET,
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offsetof(struct kvm_pt_regs, r14));
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DEFINE(VMM_PT_REGS_R2_OFFSET,
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offsetof(struct kvm_pt_regs, r2));
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DEFINE(VMM_PT_REGS_R3_OFFSET,
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offsetof(struct kvm_pt_regs, r3));
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DEFINE(VMM_PT_REGS_R16_OFFSET,
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offsetof(struct kvm_pt_regs, r16));
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DEFINE(VMM_PT_REGS_R17_OFFSET,
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offsetof(struct kvm_pt_regs, r17));
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DEFINE(VMM_PT_REGS_R18_OFFSET,
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offsetof(struct kvm_pt_regs, r18));
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DEFINE(VMM_PT_REGS_R19_OFFSET,
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offsetof(struct kvm_pt_regs, r19));
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DEFINE(VMM_PT_REGS_R20_OFFSET,
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offsetof(struct kvm_pt_regs, r20));
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DEFINE(VMM_PT_REGS_R21_OFFSET,
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offsetof(struct kvm_pt_regs, r21));
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DEFINE(VMM_PT_REGS_R22_OFFSET,
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offsetof(struct kvm_pt_regs, r22));
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DEFINE(VMM_PT_REGS_R23_OFFSET,
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offsetof(struct kvm_pt_regs, r23));
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DEFINE(VMM_PT_REGS_R24_OFFSET,
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offsetof(struct kvm_pt_regs, r24));
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DEFINE(VMM_PT_REGS_R25_OFFSET,
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offsetof(struct kvm_pt_regs, r25));
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DEFINE(VMM_PT_REGS_R26_OFFSET,
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offsetof(struct kvm_pt_regs, r26));
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DEFINE(VMM_PT_REGS_R27_OFFSET,
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offsetof(struct kvm_pt_regs, r27));
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DEFINE(VMM_PT_REGS_R28_OFFSET,
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offsetof(struct kvm_pt_regs, r28));
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DEFINE(VMM_PT_REGS_R29_OFFSET,
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offsetof(struct kvm_pt_regs, r29));
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DEFINE(VMM_PT_REGS_R30_OFFSET,
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offsetof(struct kvm_pt_regs, r30));
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DEFINE(VMM_PT_REGS_R31_OFFSET,
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offsetof(struct kvm_pt_regs, r31));
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DEFINE(VMM_PT_REGS_AR_CCV_OFFSET,
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offsetof(struct kvm_pt_regs, ar_ccv));
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DEFINE(VMM_PT_REGS_F6_OFFSET,
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offsetof(struct kvm_pt_regs, f6));
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DEFINE(VMM_PT_REGS_F7_OFFSET,
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offsetof(struct kvm_pt_regs, f7));
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DEFINE(VMM_PT_REGS_F8_OFFSET,
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offsetof(struct kvm_pt_regs, f8));
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DEFINE(VMM_PT_REGS_F9_OFFSET,
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offsetof(struct kvm_pt_regs, f9));
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DEFINE(VMM_PT_REGS_F10_OFFSET,
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offsetof(struct kvm_pt_regs, f10));
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DEFINE(VMM_PT_REGS_F11_OFFSET,
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offsetof(struct kvm_pt_regs, f11));
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DEFINE(VMM_PT_REGS_R4_OFFSET,
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offsetof(struct kvm_pt_regs, r4));
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DEFINE(VMM_PT_REGS_R5_OFFSET,
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offsetof(struct kvm_pt_regs, r5));
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DEFINE(VMM_PT_REGS_R6_OFFSET,
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offsetof(struct kvm_pt_regs, r6));
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DEFINE(VMM_PT_REGS_R7_OFFSET,
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offsetof(struct kvm_pt_regs, r7));
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DEFINE(VMM_PT_REGS_EML_UNAT_OFFSET,
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offsetof(struct kvm_pt_regs, eml_unat));
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DEFINE(VMM_VCPU_IIPA_OFFSET,
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offsetof(struct kvm_vcpu, arch.cr_iipa));
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DEFINE(VMM_VCPU_OPCODE_OFFSET,
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offsetof(struct kvm_vcpu, arch.opcode));
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DEFINE(VMM_VCPU_CAUSE_OFFSET, offsetof(struct kvm_vcpu, arch.cause));
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DEFINE(VMM_VCPU_ISR_OFFSET,
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offsetof(struct kvm_vcpu, arch.cr_isr));
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DEFINE(VMM_PT_REGS_R16_SLOT,
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(((offsetof(struct kvm_pt_regs, r16)
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- sizeof(struct kvm_pt_regs)) >> 3) & 0x3f));
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DEFINE(VMM_VCPU_MODE_FLAGS_OFFSET,
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offsetof(struct kvm_vcpu, arch.mode_flags));
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DEFINE(VMM_VCPU_GP_OFFSET, offsetof(struct kvm_vcpu, arch.__gp));
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BLANK();
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DEFINE(VMM_VPD_BASE_OFFSET, offsetof(struct kvm_vcpu, arch.vpd));
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DEFINE(VMM_VPD_VIFS_OFFSET, offsetof(struct vpd, ifs));
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DEFINE(VMM_VLSAPIC_INSVC_BASE_OFFSET,
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offsetof(struct kvm_vcpu, arch.insvc[0]));
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DEFINE(VMM_VPD_VPTA_OFFSET, offsetof(struct vpd, pta));
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DEFINE(VMM_VPD_VPSR_OFFSET, offsetof(struct vpd, vpsr));
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DEFINE(VMM_CTX_R4_OFFSET, offsetof(union context, gr[4]));
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DEFINE(VMM_CTX_R5_OFFSET, offsetof(union context, gr[5]));
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DEFINE(VMM_CTX_R12_OFFSET, offsetof(union context, gr[12]));
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DEFINE(VMM_CTX_R13_OFFSET, offsetof(union context, gr[13]));
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DEFINE(VMM_CTX_KR0_OFFSET, offsetof(union context, ar[0]));
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DEFINE(VMM_CTX_KR1_OFFSET, offsetof(union context, ar[1]));
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DEFINE(VMM_CTX_B0_OFFSET, offsetof(union context, br[0]));
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DEFINE(VMM_CTX_B1_OFFSET, offsetof(union context, br[1]));
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DEFINE(VMM_CTX_B2_OFFSET, offsetof(union context, br[2]));
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DEFINE(VMM_CTX_RR0_OFFSET, offsetof(union context, rr[0]));
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DEFINE(VMM_CTX_RSC_OFFSET, offsetof(union context, ar[16]));
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DEFINE(VMM_CTX_BSPSTORE_OFFSET, offsetof(union context, ar[18]));
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DEFINE(VMM_CTX_RNAT_OFFSET, offsetof(union context, ar[19]));
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DEFINE(VMM_CTX_FCR_OFFSET, offsetof(union context, ar[21]));
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DEFINE(VMM_CTX_EFLAG_OFFSET, offsetof(union context, ar[24]));
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DEFINE(VMM_CTX_CFLG_OFFSET, offsetof(union context, ar[27]));
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DEFINE(VMM_CTX_FSR_OFFSET, offsetof(union context, ar[28]));
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DEFINE(VMM_CTX_FIR_OFFSET, offsetof(union context, ar[29]));
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DEFINE(VMM_CTX_FDR_OFFSET, offsetof(union context, ar[30]));
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DEFINE(VMM_CTX_UNAT_OFFSET, offsetof(union context, ar[36]));
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DEFINE(VMM_CTX_FPSR_OFFSET, offsetof(union context, ar[40]));
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DEFINE(VMM_CTX_PFS_OFFSET, offsetof(union context, ar[64]));
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DEFINE(VMM_CTX_LC_OFFSET, offsetof(union context, ar[65]));
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DEFINE(VMM_CTX_DCR_OFFSET, offsetof(union context, cr[0]));
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DEFINE(VMM_CTX_IVA_OFFSET, offsetof(union context, cr[2]));
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DEFINE(VMM_CTX_PTA_OFFSET, offsetof(union context, cr[8]));
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DEFINE(VMM_CTX_IBR0_OFFSET, offsetof(union context, ibr[0]));
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DEFINE(VMM_CTX_DBR0_OFFSET, offsetof(union context, dbr[0]));
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DEFINE(VMM_CTX_F2_OFFSET, offsetof(union context, fr[2]));
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DEFINE(VMM_CTX_F3_OFFSET, offsetof(union context, fr[3]));
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DEFINE(VMM_CTX_F32_OFFSET, offsetof(union context, fr[32]));
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DEFINE(VMM_CTX_F33_OFFSET, offsetof(union context, fr[33]));
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DEFINE(VMM_CTX_PKR0_OFFSET, offsetof(union context, pkr[0]));
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DEFINE(VMM_CTX_PSR_OFFSET, offsetof(union context, psr));
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BLANK();
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}
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