255 lines
6 KiB
C
255 lines
6 KiB
C
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/*
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2412 CPU Frequency scalling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/cpufreq.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/s3c2412.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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/* our clock resources. */
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static struct clk *xtal;
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static struct clk *fclk;
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static struct clk *hclk;
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static struct clk *armclk;
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/* HDIV: 1, 2, 3, 4, 6, 8 */
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static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
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{
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unsigned int hdiv, pdiv, armdiv, dvs;
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unsigned long hclk, fclk, armclk, armdiv_clk;
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unsigned long hclk_max;
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fclk = cfg->freq.fclk;
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armclk = cfg->freq.armclk;
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hclk_max = cfg->max.hclk;
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/* We can't run hclk above armclk as at the best we have to
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* have armclk and hclk in dvs mode. */
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if (hclk_max > armclk)
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hclk_max = armclk;
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s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
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__func__, fclk, armclk, hclk_max);
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s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
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__func__, cfg->freq.fclk, cfg->freq.armclk,
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cfg->freq.hclk, cfg->freq.pclk);
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armdiv = fclk / armclk;
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if (armdiv < 1)
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armdiv = 1;
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if (armdiv > 2)
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armdiv = 2;
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cfg->divs.arm_divisor = armdiv;
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armdiv_clk = fclk / armdiv;
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hdiv = armdiv_clk / hclk_max;
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if (hdiv < 1)
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hdiv = 1;
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cfg->freq.hclk = hclk = armdiv_clk / hdiv;
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/* set dvs depending on whether we reached armclk or not. */
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cfg->divs.dvs = dvs = armclk < armdiv_clk;
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/* update the actual armclk we achieved. */
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cfg->freq.armclk = dvs ? hclk : armdiv_clk;
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s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
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__func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
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if (hdiv > 4)
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goto invalid;
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pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
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if ((hclk / pdiv) > cfg->max.pclk)
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pdiv++;
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cfg->freq.pclk = hclk / pdiv;
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s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
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if (pdiv > 2)
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goto invalid;
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pdiv *= hdiv;
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/* store the result, and then return */
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cfg->divs.h_divisor = hdiv * armdiv;
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cfg->divs.p_divisor = pdiv * armdiv;
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return 0;
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invalid:
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return -EINVAL;
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}
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static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
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{
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unsigned long clkdiv;
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unsigned long olddiv;
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olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
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/* clear off current clock info */
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clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
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clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
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clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
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if (cfg->divs.arm_divisor == 2)
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clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
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clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
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if (cfg->divs.p_divisor != cfg->divs.h_divisor)
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clkdiv |= S3C2412_CLKDIVN_PDIVN;
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s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
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__raw_writel(clkdiv, S3C2410_CLKDIVN);
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clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
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}
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static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
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{
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struct s3c_cpufreq_board *board = cfg->board;
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unsigned long refresh;
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s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
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board->refresh, cfg->freq.hclk);
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/* Reduce both the refresh time (in ns) and the frequency (in MHz)
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* by 10 each to ensure that we do not overflow 32 bit numbers. This
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* should work for HCLK up to 133MHz and refresh period up to 30usec.
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*/
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refresh = (board->refresh / 10);
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refresh *= (cfg->freq.hclk / 100);
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refresh /= (1 * 1000 * 1000); /* 10^6 */
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s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
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__raw_writel(refresh, S3C2412_REFRESH);
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}
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/* set the default cpu frequency information, based on an 200MHz part
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* as we have no other way of detecting the speed rating in software.
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*/
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static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
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.max = {
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.fclk = 200000000,
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.hclk = 100000000,
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.pclk = 50000000,
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},
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.latency = 5000000, /* 5ms */
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.locktime_m = 150,
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.locktime_u = 150,
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.locktime_bits = 16,
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.name = "s3c2412",
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.set_refresh = s3c2412_cpufreq_setrefresh,
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.set_divs = s3c2412_cpufreq_setdivs,
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.calc_divs = s3c2412_cpufreq_calcdivs,
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.calc_iotiming = s3c2412_iotiming_calc,
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.set_iotiming = s3c2412_iotiming_set,
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.get_iotiming = s3c2412_iotiming_get,
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.debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
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};
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static int s3c2412_cpufreq_add(struct device *dev,
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struct subsys_interface *sif)
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{
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unsigned long fclk_rate;
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hclk = clk_get(NULL, "hclk");
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if (IS_ERR(hclk)) {
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printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
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return -ENOENT;
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}
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fclk = clk_get(NULL, "fclk");
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if (IS_ERR(fclk)) {
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printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
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goto err_fclk;
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}
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fclk_rate = clk_get_rate(fclk);
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if (fclk_rate > 200000000) {
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printk(KERN_INFO
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"%s: fclk %ld MHz, assuming 266MHz capable part\n",
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__func__, fclk_rate / 1000000);
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s3c2412_cpufreq_info.max.fclk = 266000000;
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s3c2412_cpufreq_info.max.hclk = 133000000;
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s3c2412_cpufreq_info.max.pclk = 66000000;
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}
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armclk = clk_get(NULL, "armclk");
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if (IS_ERR(armclk)) {
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printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
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goto err_armclk;
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}
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xtal = clk_get(NULL, "xtal");
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if (IS_ERR(xtal)) {
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printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
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goto err_xtal;
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}
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return s3c_cpufreq_register(&s3c2412_cpufreq_info);
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err_xtal:
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clk_put(armclk);
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err_armclk:
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clk_put(fclk);
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err_fclk:
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clk_put(hclk);
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return -ENOENT;
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}
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static struct subsys_interface s3c2412_cpufreq_interface = {
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.name = "s3c2412_cpufreq",
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.subsys = &s3c2412_subsys,
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.add_dev = s3c2412_cpufreq_add,
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};
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static int s3c2412_cpufreq_init(void)
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{
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return subsys_interface_register(&s3c2412_cpufreq_interface);
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}
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arch_initcall(s3c2412_cpufreq_init);
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