461 lines
12 KiB
C
461 lines
12 KiB
C
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/*
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* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/export.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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#define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
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#define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
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#define DC_EVT_NF 0
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#define DC_EVT_NL 1
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#define DC_EVT_EOF 2
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#define DC_EVT_NFIELD 3
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#define DC_EVT_EOL 4
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#define DC_EVT_EOFIELD 5
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#define DC_EVT_NEW_ADDR 6
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#define DC_EVT_NEW_CHAN 7
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#define DC_EVT_NEW_DATA 8
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#define DC_EVT_NEW_ADDR_W_0 0
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#define DC_EVT_NEW_ADDR_W_1 1
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#define DC_EVT_NEW_CHAN_W_0 2
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#define DC_EVT_NEW_CHAN_W_1 3
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#define DC_EVT_NEW_DATA_W_0 4
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#define DC_EVT_NEW_DATA_W_1 5
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#define DC_EVT_NEW_ADDR_R_0 6
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#define DC_EVT_NEW_ADDR_R_1 7
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#define DC_EVT_NEW_CHAN_R_0 8
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#define DC_EVT_NEW_CHAN_R_1 9
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#define DC_EVT_NEW_DATA_R_0 10
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#define DC_EVT_NEW_DATA_R_1 11
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#define DC_WR_CH_CONF 0x0
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#define DC_WR_CH_ADDR 0x4
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#define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
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#define DC_GEN 0xd4
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#define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
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#define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
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#define DC_STAT 0x1c8
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#define WROD(lf) (0x18 | ((lf) << 1))
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#define WRG 0x01
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#define WCLK 0xc9
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#define SYNC_WAVE 0
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#define NULL_WAVE (-1)
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#define DC_GEN_SYNC_1_6_SYNC (2 << 1)
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#define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
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#define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
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#define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
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#define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
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#define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
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#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
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#define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
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#define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
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#define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
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#define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
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#define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
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#define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
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#define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
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#define IPU_DC_NUM_CHANNELS 10
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struct ipu_dc_priv;
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enum ipu_dc_map {
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IPU_DC_MAP_RGB24,
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IPU_DC_MAP_RGB565,
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IPU_DC_MAP_GBR24, /* TVEv2 */
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IPU_DC_MAP_BGR666,
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IPU_DC_MAP_LVDS666,
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IPU_DC_MAP_BGR24,
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};
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struct ipu_dc {
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/* The display interface number assigned to this dc channel */
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unsigned int di;
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void __iomem *base;
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struct ipu_dc_priv *priv;
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int chno;
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bool in_use;
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};
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struct ipu_dc_priv {
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void __iomem *dc_reg;
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void __iomem *dc_tmpl_reg;
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struct ipu_soc *ipu;
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struct device *dev;
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struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
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struct mutex mutex;
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struct completion comp;
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int dc_irq;
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int dp_irq;
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};
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static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
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{
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u32 reg;
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reg = readl(dc->base + DC_RL_CH(event));
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reg &= ~(0xffff << (16 * (event & 0x1)));
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reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
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writel(reg, dc->base + DC_RL_CH(event));
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}
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static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
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int map, int wave, int glue, int sync, int stop)
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{
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struct ipu_dc_priv *priv = dc->priv;
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u32 reg1, reg2;
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if (opcode == WCLK) {
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reg1 = (operand << 20) & 0xfff00000;
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reg2 = operand >> 12 | opcode << 1 | stop << 9;
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} else if (opcode == WRG) {
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reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
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reg2 = operand >> 17 | opcode << 7 | stop << 9;
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} else {
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reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
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reg2 = operand >> 12 | opcode << 4 | stop << 9;
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}
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writel(reg1, priv->dc_tmpl_reg + word * 8);
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writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
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}
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static int ipu_pixfmt_to_map(u32 fmt)
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{
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switch (fmt) {
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case V4L2_PIX_FMT_RGB24:
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return IPU_DC_MAP_RGB24;
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case V4L2_PIX_FMT_RGB565:
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return IPU_DC_MAP_RGB565;
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case IPU_PIX_FMT_GBR24:
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return IPU_DC_MAP_GBR24;
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case V4L2_PIX_FMT_BGR666:
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return IPU_DC_MAP_BGR666;
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case v4l2_fourcc('L', 'V', 'D', '6'):
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return IPU_DC_MAP_LVDS666;
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case V4L2_PIX_FMT_BGR24:
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return IPU_DC_MAP_BGR24;
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default:
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return -EINVAL;
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}
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}
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int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
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u32 pixel_fmt, u32 width)
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{
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struct ipu_dc_priv *priv = dc->priv;
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u32 reg = 0;
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int map;
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dc->di = ipu_di_get_num(di);
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map = ipu_pixfmt_to_map(pixel_fmt);
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if (map < 0) {
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dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
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return map;
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}
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if (interlaced) {
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dc_link_event(dc, DC_EVT_NL, 0, 3);
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dc_link_event(dc, DC_EVT_EOL, 0, 2);
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dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
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/* Init template microcode */
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dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
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} else {
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if (dc->di) {
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dc_link_event(dc, DC_EVT_NL, 2, 3);
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dc_link_event(dc, DC_EVT_EOL, 3, 2);
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dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
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/* Init template microcode */
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dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
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dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
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dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
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dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
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} else {
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dc_link_event(dc, DC_EVT_NL, 5, 3);
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dc_link_event(dc, DC_EVT_EOL, 6, 2);
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dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
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/* Init template microcode */
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dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
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dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
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dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
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dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
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}
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}
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dc_link_event(dc, DC_EVT_NF, 0, 0);
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dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
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dc_link_event(dc, DC_EVT_EOF, 0, 0);
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dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
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dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
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dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
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reg = readl(dc->base + DC_WR_CH_CONF);
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if (interlaced)
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reg |= DC_WR_CH_CONF_FIELD_MODE;
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else
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reg &= ~DC_WR_CH_CONF_FIELD_MODE;
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writel(reg, dc->base + DC_WR_CH_CONF);
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writel(0x0, dc->base + DC_WR_CH_ADDR);
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writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
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void ipu_dc_enable(struct ipu_soc *ipu)
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{
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ipu_module_enable(ipu, IPU_CONF_DC_EN);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_enable);
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void ipu_dc_enable_channel(struct ipu_dc *dc)
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{
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int di;
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u32 reg;
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di = dc->di;
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reg = readl(dc->base + DC_WR_CH_CONF);
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reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
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writel(reg, dc->base + DC_WR_CH_CONF);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
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static irqreturn_t dc_irq_handler(int irq, void *dev_id)
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{
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struct ipu_dc *dc = dev_id;
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u32 reg;
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reg = readl(dc->base + DC_WR_CH_CONF);
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reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
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writel(reg, dc->base + DC_WR_CH_CONF);
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/* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */
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complete(&dc->priv->comp);
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return IRQ_HANDLED;
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}
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void ipu_dc_disable_channel(struct ipu_dc *dc)
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{
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struct ipu_dc_priv *priv = dc->priv;
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int irq, ret;
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u32 val;
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/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
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if (dc->chno == 1)
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irq = priv->dc_irq;
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else if (dc->chno == 5)
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irq = priv->dp_irq;
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else
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return;
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init_completion(&priv->comp);
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enable_irq(irq);
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ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
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disable_irq(irq);
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if (ret <= 0) {
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dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
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val = readl(dc->base + DC_WR_CH_CONF);
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val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
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writel(val, dc->base + DC_WR_CH_CONF);
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}
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}
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EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
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void ipu_dc_disable(struct ipu_soc *ipu)
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{
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ipu_module_disable(ipu, IPU_CONF_DC_EN);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_disable);
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static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
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int byte_num, int offset, int mask)
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{
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int ptr = map * 3 + byte_num;
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u32 reg;
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reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
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reg &= ~(0xffff << (16 * (ptr & 0x1)));
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reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
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writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
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reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
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reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
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reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
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writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
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}
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static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
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{
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u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
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writel(reg & ~(0xffff << (16 * (map & 0x1))),
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priv->dc_reg + DC_MAP_CONF_PTR(map));
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}
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struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
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{
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struct ipu_dc_priv *priv = ipu->dc_priv;
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struct ipu_dc *dc;
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if (channel >= IPU_DC_NUM_CHANNELS)
|
||
|
|
return ERR_PTR(-ENODEV);
|
||
|
|
|
||
|
|
dc = &priv->channels[channel];
|
||
|
|
|
||
|
|
mutex_lock(&priv->mutex);
|
||
|
|
|
||
|
|
if (dc->in_use) {
|
||
|
|
mutex_unlock(&priv->mutex);
|
||
|
|
return ERR_PTR(-EBUSY);
|
||
|
|
}
|
||
|
|
|
||
|
|
dc->in_use = true;
|
||
|
|
|
||
|
|
mutex_unlock(&priv->mutex);
|
||
|
|
|
||
|
|
return dc;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(ipu_dc_get);
|
||
|
|
|
||
|
|
void ipu_dc_put(struct ipu_dc *dc)
|
||
|
|
{
|
||
|
|
struct ipu_dc_priv *priv = dc->priv;
|
||
|
|
|
||
|
|
mutex_lock(&priv->mutex);
|
||
|
|
dc->in_use = false;
|
||
|
|
mutex_unlock(&priv->mutex);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(ipu_dc_put);
|
||
|
|
|
||
|
|
int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
|
||
|
|
unsigned long base, unsigned long template_base)
|
||
|
|
{
|
||
|
|
struct ipu_dc_priv *priv;
|
||
|
|
static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
|
||
|
|
0x78, 0, 0x94, 0xb4};
|
||
|
|
int i, ret;
|
||
|
|
|
||
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||
|
|
if (!priv)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
mutex_init(&priv->mutex);
|
||
|
|
|
||
|
|
priv->dev = dev;
|
||
|
|
priv->ipu = ipu;
|
||
|
|
priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
|
||
|
|
priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
|
||
|
|
if (!priv->dc_reg || !priv->dc_tmpl_reg)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
|
||
|
|
priv->channels[i].chno = i;
|
||
|
|
priv->channels[i].priv = priv;
|
||
|
|
priv->channels[i].base = priv->dc_reg + channel_offsets[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
|
||
|
|
if (!priv->dc_irq)
|
||
|
|
return -EINVAL;
|
||
|
|
ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
|
||
|
|
&priv->channels[1]);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
disable_irq(priv->dc_irq);
|
||
|
|
priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
|
||
|
|
if (!priv->dp_irq)
|
||
|
|
return -EINVAL;
|
||
|
|
ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
|
||
|
|
&priv->channels[5]);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
disable_irq(priv->dp_irq);
|
||
|
|
|
||
|
|
writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
|
||
|
|
DC_WR_CH_CONF_PROG_DI_ID,
|
||
|
|
priv->channels[1].base + DC_WR_CH_CONF);
|
||
|
|
writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
|
||
|
|
priv->channels[5].base + DC_WR_CH_CONF);
|
||
|
|
|
||
|
|
writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
|
||
|
|
priv->dc_reg + DC_GEN);
|
||
|
|
|
||
|
|
ipu->dc_priv = priv;
|
||
|
|
|
||
|
|
dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
|
||
|
|
base, template_base);
|
||
|
|
|
||
|
|
/* rgb24 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
|
||
|
|
|
||
|
|
/* rgb565 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
|
||
|
|
|
||
|
|
/* gbr24 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
|
||
|
|
|
||
|
|
/* bgr666 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
|
||
|
|
|
||
|
|
/* lvds666 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
|
||
|
|
|
||
|
|
/* bgr24 */
|
||
|
|
ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
|
||
|
|
ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ipu_dc_exit(struct ipu_soc *ipu)
|
||
|
|
{
|
||
|
|
}
|