1307 lines
36 KiB
Text
1307 lines
36 KiB
Text
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config ARM64
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def_bool y
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select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
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select ARCH_HAS_ELF_RANDOMIZE
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select ARCH_HAS_SG_CHAIN
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select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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select ARCH_USE_CMPXCHG_LOCKREF
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select ARCH_SUPPORTS_ATOMIC_RMW
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
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select ARCH_WANT_FRAME_POINTERS
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select ARCH_HAVE_CUSTOM_GPIO_H
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select ARM_AMBA
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select ARM_ARCH_TIMER
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select ARM_GIC
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select AUDIT_ARCH_COMPAT_GENERIC
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select ARM_GIC_V3
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK if !ARCH_MSM
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select CPU_PM if (SUSPEND || CPU_IDLE)
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select DCACHE_WORD_ACCESS
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select GENERIC_ALLOCATOR
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select EDAC_SUPPORT
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select GENERIC_CLOCKEVENTS
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_CPU_AUTOPROBE
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select GENERIC_EARLY_IOREMAP
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select GENERIC_IOMAP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_SCHED_CLOCK
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_STRNCPY_FROM_USER
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select GENERIC_STRNLEN_USER
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select GENERIC_TIME_VSYSCALL
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select HANDLE_DOMAIN_IRQ
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select HARDIRQS_SW_RESEND
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select HAVE_ALIGNED_STRUCT_PAGE if SLUB
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_JUMP_LABEL
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select HAVE_ARCH_KGDB
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_BPF_JIT
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select HAVE_C_RECORDMCOUNT
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select HAVE_CC_STACKPROTECTOR
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select HAVE_CMPXCHG_DOUBLE
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select HAVE_DEBUG_BUGVERBOSE
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_API_DEBUG
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select HAVE_DMA_ATTRS
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select HAVE_DMA_CONTIGUOUS
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select HAVE_DYNAMIC_FTRACE
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select HAVE_EFFICIENT_UNALIGNED_ACCESS
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select HAVE_FTRACE_MCOUNT_RECORD
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select HAVE_FUNCTION_TRACER
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select HAVE_FUNCTION_GRAPH_TRACER
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select HAVE_GENERIC_DMA_COHERENT
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select HAVE_IRQ_TIME_ACCOUNTING
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select HAVE_MEMBLOCK
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select HAVE_PATA_PLATFORM
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select HAVE_PERF_EVENTS
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_RCU_TABLE_FREE
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select HAVE_SYSCALL_TRACEPOINTS
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select IRQ_DOMAIN
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select MODULES_USE_ELF_RELA
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select NO_BOOTMEM
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select OF
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select OF_EARLY_FLATTREE
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select OF_RESERVED_MEM
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select PERF_USE_VMALLOC
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select POWER_RESET
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select POWER_SUPPLY
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select RTC_LIB
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select SPARSE_IRQ
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select SYSCTL_EXCEPTION_TRACE
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select HAVE_CONTEXT_TRACKING
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select MSM_JTAGV8 if CORESIGHT_ETMV4
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help
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ARM 64-bit (AArch64) Linux support.
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config 64BIT
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def_bool y
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config ARCH_PHYS_ADDR_T_64BIT
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def_bool y
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config MMU
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def_bool y
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config NO_IOPORT_MAP
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def_bool y if !PCI
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config STACKTRACE_SUPPORT
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def_bool y
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config LOCKDEP_SUPPORT
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def_bool y
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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config RWSEM_XCHGADD_ALGORITHM
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def_bool y
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config GENERIC_BUG
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def_bool y
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depends on BUG
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config GENERIC_HWEIGHT
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def_bool y
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config GENERIC_CSUM
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def_bool y
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config GENERIC_CALIBRATE_DELAY
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def_bool y
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config ZONE_DMA
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def_bool y
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config HAVE_GENERIC_RCU_GUP
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def_bool y
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config ARCH_DMA_ADDR_T_64BIT
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def_bool y
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config NEED_DMA_MAP_STATE
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def_bool y
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config NEED_SG_DMA_LENGTH
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def_bool y
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config ARM64_DMA_USE_IOMMU
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bool
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select ARM_HAS_SG_CHAIN
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select NEED_SG_DMA_LENGTH
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if ARM64_DMA_USE_IOMMU
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config ARM64_DMA_IOMMU_ALIGNMENT
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int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
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range 4 9
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default 8
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help
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DMA mapping framework by default aligns all buffers to the smallest
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PAGE_SIZE order which is greater than or equal to the requested buffer
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size. This works well for buffers up to a few hundreds kilobytes, but
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for larger buffers it just a waste of address space. Drivers which has
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relatively small addressing window (like 64Mib) might run out of
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virtual space with just a few allocations.
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With this parameter you can specify the maximum PAGE_SIZE order for
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DMA IOMMU buffers. Larger buffers will be aligned only to this
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specified order. The order is expressed as a power of two multiplied
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by the PAGE_SIZE.
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endif
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config SWIOTLB
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def_bool y
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config IOMMU_HELPER
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def_bool SWIOTLB
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config KERNEL_MODE_NEON
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def_bool y
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config FIX_EARLYCON_MEM
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def_bool y
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source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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menu "Platform selection"
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select ARCH_REQUIRE_GPIOLIB
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select COMMON_CLK_VERSATILE
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select POWER_RESET_VEXPRESS
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select VEXPRESS_CONFIG
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_MSM
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bool "Qualcomm Platforms"
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select HAVE_CLK
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select HAVE_CLK_PREPARE
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select MSM_IRQ
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select PINCTRL
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select SOC_BUS
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select PM_OPP
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select PCI
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select PM_DEVFREQ
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select MSM_DEVFREQ_DEVBW
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select MSM_BIMC_BWMON
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select MSMCCI_HWMON
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select MSM_M4M_HWMON
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select DEVFREQ_GOV_MSM_BW_HWMON
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select DEVFREQ_GOV_MSM_CACHE_HWMON
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select DEVFREQ_SIMPLE_DEV
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select ARCH_HAS_OPP
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select THERMAL_WRITABLE_TRIPS
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select CPU_FREQ_MSM
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select ARM_MEMLAT_MON
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select DEVFREQ_GOV_MEMLAT
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_MSM8916
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bool "Enable Support for Qualcomm MSM8916"
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depends on ARCH_MSM
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help
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This enables support for the MSM8916 chipset. If you don't
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know what to do here, say N
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config ARCH_MSMTITANIUM
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bool "Enable Support for Qualcomm Technologies Inc MSMTITANIUM"
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depends on ARCH_MSM
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help
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This enables support for the MSMTITANIUM chipset. If you don't
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know what to do here, say N
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config ARCH_MSMTHORIUM
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bool "Enable Support for Qualcomm Technologies Inc MSMTHORIUM"
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depends on ARCH_MSM
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help
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This enables support for the MSMTHORIUM chipset. If you don't
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know what to do here, say N
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config ARCH_MSM8996
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bool "Enable Support for Qualcomm MSM8996"
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depends on ARCH_MSM
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help
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This enables support for the MSM8996 chipset. If you don't
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know what to do here, say N
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config ARCH_MSMCOBALT
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bool "Enable Support for Qualcomm MSMCOBALT"
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depends on ARCH_MSM
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help
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This enables support for the MSMCOBALT chipset. If you do not
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wish to build a kernel that runs on this chipset, say 'N' here.
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config ARCH_MSM8994_V1_TLBI_WA
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bool "Enable MSM8994 v1 TLBI workaround"
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depends on ARCH_MSM8994
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help
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This enables support for the MSM8994 v1 TLBI workaround. This
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workaround is required for MSM8994 V1 revision where the
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[39:38] bits of VA are tied to zero and due to which TLBI
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operations with VA or ASID will not work.
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endmenu
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config SEC_FACTORY
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bool "when it comes to sec factory mode"
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default n
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help
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It will support a sec factory mode
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config SEC_HEROQLTE_PROJECT
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depends on ARCH_MSM8996
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default n
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bool "Samsung HEROQLTE Project"
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help
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Support for Samsung HEROQLTE Project
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config MACH_HEROQLTE_ACG
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE USA ACG"
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help
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Support for Samsung HEROQLTE USA ACG device.
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config MACH_HEROQLTE_ATT
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE USA ATT"
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help
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Support for Samsung HEROQLTE USA ATT device.
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config MACH_HEROQLTE_CHNZC
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depends on SEC_HEROQLTE_PROJECT
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select PROC_TASK_STATE_CHN_ORDER
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default n
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bool "Samsung HEROQLTE CHN OPEN"
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help
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Support for Samsung HEROQLTE CHN OPEN device.
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config MACH_HEROQLTE_DCM
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE JPN DCM"
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help
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Support for Samsung HEROQLTE JPN DCM device.
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config MACH_HEROQLTE_KDI
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE JPN KDI"
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help
|
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Support for Samsung HEROQLTE JPN KDI device.
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config MACH_HEROQLTE_SPR
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE USA SPR"
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help
|
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Support for Samsung HEROQLTE USA SPR device.
|
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config MACH_HEROQLTE_TMO
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depends on SEC_HEROQLTE_PROJECT
|
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default n
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bool "Samsung HEROQLTE USA TMO"
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help
|
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Support for Samsung HEROQLTE USA TMO device.
|
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config MACH_HEROQLTE_USC
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depends on SEC_HEROQLTE_PROJECT
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default n
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bool "Samsung HEROQLTE USA USC"
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help
|
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Support for Samsung HEROQLTE USA USC device.
|
||
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config MACH_HEROQLTE_VZW
|
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depends on SEC_HEROQLTE_PROJECT
|
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default n
|
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bool "Samsung HEROQLTE USA VZW"
|
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help
|
||
|
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Support for Samsung HEROQLTE USA VZW device.
|
||
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|
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config MACH_HEROQLTE_MTR
|
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depends on SEC_HEROQLTE_PROJECT
|
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|
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default n
|
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|
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bool "Samsung HEROQLTE USA MTR"
|
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|
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help
|
||
|
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Support for Samsung HEROQLTE USA MTR device.
|
||
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|
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config SEC_HERO2QLTE_PROJECT
|
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depends on ARCH_MSM8996
|
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default n
|
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bool "Samsung HERO2QLTE Project"
|
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|
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help
|
||
|
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Support for Samsung HERO2QLTE Project
|
||
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|
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config MACH_HERO2QLTE_ATT
|
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depends on SEC_HERO2QLTE_PROJECT
|
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default n
|
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bool "Samsung HERO2QLTE USA ATT"
|
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|
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help
|
||
|
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Support for Samsung HERO2QLTE USA ATT device.
|
||
|
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|
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config MACH_HERO2QLTE_CHNZC
|
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|
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depends on SEC_HERO2QLTE_PROJECT
|
||
|
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select PROC_TASK_STATE_CHN_ORDER
|
||
|
|
default n
|
||
|
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bool "Samsung HERO2QLTE CHN OPEN"
|
||
|
|
help
|
||
|
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Support for Samsung HERO2QLTE CHN OPEN device.
|
||
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|
||
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config MACH_HERO2QLTE_SPR
|
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|
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depends on SEC_HERO2QLTE_PROJECT
|
||
|
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default n
|
||
|
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bool "Samsung HERO2QLTE USA SPR"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE USA SPR device.
|
||
|
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|
||
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config MACH_HERO2QLTE_TMO
|
||
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depends on SEC_HERO2QLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung HERO2QLTE USA TMO"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE USA TMO device.
|
||
|
|
|
||
|
|
config MACH_HERO2QLTE_USC
|
||
|
|
depends on SEC_HERO2QLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung HERO2QLTE USA USC"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE USA USC device.
|
||
|
|
|
||
|
|
config MACH_HERO2QLTE_VZW
|
||
|
|
depends on SEC_HERO2QLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung HERO2QLTE USA VZW"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE USA VZW device.
|
||
|
|
|
||
|
|
config MACH_HERO2QLTE_DCM
|
||
|
|
depends on SEC_HERO2QLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung HERO2QLTE JPN DCM"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE JPN DCM device.
|
||
|
|
|
||
|
|
config MACH_HERO2QLTE_KDI
|
||
|
|
depends on SEC_HERO2QLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung HERO2QLTE JPN KDI"
|
||
|
|
help
|
||
|
|
Support for Samsung HERO2QLTE JPN KDI device.
|
||
|
|
|
||
|
|
config SEC_AEROQLTE_PROJECT
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
default n
|
||
|
|
bool "Samsung AEROQLTE Project"
|
||
|
|
help
|
||
|
|
Support for Samsung AEROQLTE Project
|
||
|
|
|
||
|
|
config MACH_AEROQLTE_VZW
|
||
|
|
depends on SEC_AEROQLTE_PROJECT
|
||
|
|
default n
|
||
|
|
bool "Samsung AEROQLTE USA VZW"
|
||
|
|
help
|
||
|
|
Support for Samsung AEROQLTE USA VZW device.
|
||
|
|
|
||
|
|
config SEC_LUCKYQLTE_DSC_PROJECT
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
default n
|
||
|
|
bool "Samsung LUCKYQLTE DSC Project"
|
||
|
|
help
|
||
|
|
Support for Samsung LUCKYQLTE DSC Project
|
||
|
|
|
||
|
|
config SAMSUNG_PRODUCT_SHIP
|
||
|
|
bool "set up for product shipping"
|
||
|
|
default n
|
||
|
|
|
||
|
|
menu "Bus support"
|
||
|
|
|
||
|
|
config ARM_AMBA
|
||
|
|
bool
|
||
|
|
|
||
|
|
config PCI
|
||
|
|
bool "PCI support"
|
||
|
|
help
|
||
|
|
This feature enables support for PCI bus system. If you say Y
|
||
|
|
here, the kernel will include drivers and infrastructure code
|
||
|
|
to support PCI bus devices.
|
||
|
|
|
||
|
|
config PCI_DOMAINS
|
||
|
|
def_bool PCI
|
||
|
|
|
||
|
|
config PCI_DOMAINS_GENERIC
|
||
|
|
def_bool PCI
|
||
|
|
|
||
|
|
config PCI_SYSCALL
|
||
|
|
def_bool PCI
|
||
|
|
|
||
|
|
source "drivers/pci/Kconfig"
|
||
|
|
source "drivers/pci/pcie/Kconfig"
|
||
|
|
source "drivers/pci/hotplug/Kconfig"
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
menu "Kernel Features"
|
||
|
|
|
||
|
|
menu "ARM errata workarounds via the alternatives framework"
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_826319
|
||
|
|
bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
|
||
|
|
AXI master interface and an L2 cache.
|
||
|
|
|
||
|
|
If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
|
||
|
|
and is unable to accept a certain write via this interface, it will
|
||
|
|
not progress on read data presented on the read data channel and the
|
||
|
|
system can deadlock.
|
||
|
|
|
||
|
|
The workaround promotes data cache clean instructions to
|
||
|
|
data cache clean-and-invalidate.
|
||
|
|
Please note that this does not necessarily enable the workaround,
|
||
|
|
as it depends on the alternative framework, which will only patch
|
||
|
|
the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_827319
|
||
|
|
bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
|
||
|
|
master interface and an L2 cache.
|
||
|
|
|
||
|
|
Under certain conditions this erratum can cause a clean line eviction
|
||
|
|
to occur at the same time as another transaction to the same address
|
||
|
|
on the AMBA 5 CHI interface, which can cause data corruption if the
|
||
|
|
interconnect reorders the two transactions.
|
||
|
|
|
||
|
|
The workaround promotes data cache clean instructions to
|
||
|
|
data cache clean-and-invalidate.
|
||
|
|
Please note that this does not necessarily enable the workaround,
|
||
|
|
as it depends on the alternative framework, which will only patch
|
||
|
|
the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_824069
|
||
|
|
bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
|
||
|
|
to a coherent interconnect.
|
||
|
|
|
||
|
|
If a Cortex-A53 processor is executing a store or prefetch for
|
||
|
|
write instruction at the same time as a processor in another
|
||
|
|
cluster is executing a cache maintenance operation to the same
|
||
|
|
address, then this erratum might cause a clean cache line to be
|
||
|
|
incorrectly marked as dirty.
|
||
|
|
|
||
|
|
The workaround promotes data cache clean instructions to
|
||
|
|
data cache clean-and-invalidate.
|
||
|
|
Please note that this option does not necessarily enable the
|
||
|
|
workaround, as it depends on the alternative framework, which will
|
||
|
|
only patch the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_819472
|
||
|
|
bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
|
||
|
|
present when it is connected to a coherent interconnect.
|
||
|
|
|
||
|
|
If the processor is executing a load and store exclusive sequence at
|
||
|
|
the same time as a processor in another cluster is executing a cache
|
||
|
|
maintenance operation to the same address, then this erratum might
|
||
|
|
cause data corruption.
|
||
|
|
|
||
|
|
The workaround promotes data cache clean instructions to
|
||
|
|
data cache clean-and-invalidate.
|
||
|
|
Please note that this does not necessarily enable the workaround,
|
||
|
|
as it depends on the alternative framework, which will only patch
|
||
|
|
the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_832075
|
||
|
|
bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 832075 on Cortex-A57 parts up to r1p2.
|
||
|
|
|
||
|
|
Affected Cortex-A57 parts might deadlock when exclusive load/store
|
||
|
|
instructions to Write-Back memory are mixed with Device loads.
|
||
|
|
|
||
|
|
The workaround is to promote device loads to use Load-Acquire
|
||
|
|
semantics.
|
||
|
|
Please note that this does not necessarily enable the workaround,
|
||
|
|
as it depends on the alternative framework, which will only patch
|
||
|
|
the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
config ARM64_ERRATUM_845719
|
||
|
|
bool "Cortex-A53: 845719: a load might read incorrect data"
|
||
|
|
depends on COMPAT
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option adds an alternative code sequence to work around ARM
|
||
|
|
erratum 845719 on Cortex-A53 parts up to r0p4.
|
||
|
|
|
||
|
|
When running a compat (AArch32) userspace on an affected Cortex-A53
|
||
|
|
part, a load at EL0 from a virtual address that matches the bottom 32
|
||
|
|
bits of the virtual address used by a recent load at (AArch64) EL1
|
||
|
|
might return incorrect data.
|
||
|
|
|
||
|
|
The workaround is to write the contextidr_el1 register on exception
|
||
|
|
return to a 32-bit task.
|
||
|
|
Please note that this does not necessarily enable the workaround,
|
||
|
|
as it depends on the alternative framework, which will only patch
|
||
|
|
the kernel if an affected CPU is detected.
|
||
|
|
|
||
|
|
If unsure, say Y.
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Page size"
|
||
|
|
default ARM64_4K_PAGES
|
||
|
|
help
|
||
|
|
Page size (translation granule) configuration.
|
||
|
|
|
||
|
|
config ARM64_4K_PAGES
|
||
|
|
bool "4KB"
|
||
|
|
help
|
||
|
|
This feature enables 4KB pages support.
|
||
|
|
|
||
|
|
config ARM64_64K_PAGES
|
||
|
|
bool "64KB"
|
||
|
|
help
|
||
|
|
This feature enables 64KB pages support (4KB by default)
|
||
|
|
allowing only two levels of page tables and faster TLB
|
||
|
|
look-up. AArch32 emulation is not available when this feature
|
||
|
|
is enabled.
|
||
|
|
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
config ARM64_DCACHE_DISABLE
|
||
|
|
bool "Disable CPU Data Caches"
|
||
|
|
help
|
||
|
|
Disable CPU data cache usage by setting the SCTLR[C] bit during
|
||
|
|
kernel initialization. This will result in a considerable
|
||
|
|
performance impact, but may be useful in certain situations.
|
||
|
|
|
||
|
|
If you are not sure what to do, select 'N' here.
|
||
|
|
|
||
|
|
config ARM64_ICACHE_DISABLE
|
||
|
|
bool "Disable CPU Instruction Caches"
|
||
|
|
help
|
||
|
|
Disable CPU instruction cache usage by setting the SCTLR[I]
|
||
|
|
bit during kernel initialization. This will result in a
|
||
|
|
considerable performance impact, but may be useful in certain
|
||
|
|
situations.
|
||
|
|
|
||
|
|
If you are not sure what to do, select 'N' here.
|
||
|
|
|
||
|
|
config MSM_APP_API
|
||
|
|
bool "API support to enable / disable app settings for MSM8996"
|
||
|
|
depends on ARCH_MSM8996 && (ENABLE_FP_SIMD_SETTINGS || MSM_APP_SETTINGS)
|
||
|
|
help
|
||
|
|
Add API support to enable / disable the app settings to be used
|
||
|
|
at runtime.
|
||
|
|
|
||
|
|
If you are not sure what to do, select 'N' here.
|
||
|
|
|
||
|
|
config ENABLE_FP_SIMD_SETTINGS
|
||
|
|
bool "Enable FP(Floating Point) Settings for Qualcomm MSM8996"
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
select MSM_APP_API
|
||
|
|
help
|
||
|
|
Enable FP(Floating Point) and SIMD settings for the MSM8996 during
|
||
|
|
the execution of the aarch32 processes and disable these settings
|
||
|
|
when you switch to the aarch64 processes.
|
||
|
|
|
||
|
|
If you are not sure what to do, select 'N' here.
|
||
|
|
|
||
|
|
config MSM_APP_SETTINGS
|
||
|
|
bool "Support to enable / disable app settings for MSM8996"
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
select MSM_APP_API
|
||
|
|
help
|
||
|
|
Expose an interface used by the userspace at runtime to
|
||
|
|
enable / disable the app specific settings.
|
||
|
|
|
||
|
|
If you are not sure what to do, select 'N' here.
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Virtual address space size"
|
||
|
|
default ARM64_VA_BITS_39 if ARM64_4K_PAGES
|
||
|
|
default ARM64_VA_BITS_42 if ARM64_64K_PAGES
|
||
|
|
help
|
||
|
|
Allows choosing one of multiple possible virtual address
|
||
|
|
space sizes. The level of translation table is determined by
|
||
|
|
a combination of page size and virtual address space size.
|
||
|
|
|
||
|
|
config ARM64_VA_BITS_39
|
||
|
|
bool "39-bit"
|
||
|
|
depends on ARM64_4K_PAGES
|
||
|
|
|
||
|
|
config ARM64_VA_BITS_42
|
||
|
|
bool "42-bit"
|
||
|
|
depends on ARM64_64K_PAGES
|
||
|
|
|
||
|
|
config ARM64_VA_BITS_48
|
||
|
|
bool "48-bit"
|
||
|
|
depends on !ARM_SMMU
|
||
|
|
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
config ARM64_VA_BITS
|
||
|
|
int
|
||
|
|
default 39 if ARM64_VA_BITS_39
|
||
|
|
default 42 if ARM64_VA_BITS_42
|
||
|
|
default 48 if ARM64_VA_BITS_48
|
||
|
|
|
||
|
|
config ARM64_PGTABLE_LEVELS
|
||
|
|
int
|
||
|
|
default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
|
||
|
|
default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
|
||
|
|
default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
|
||
|
|
default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
|
||
|
|
|
||
|
|
config CPU_BIG_ENDIAN
|
||
|
|
bool "Build big-endian kernel"
|
||
|
|
help
|
||
|
|
Say Y if you plan on running a kernel in big-endian mode.
|
||
|
|
|
||
|
|
config ARM64_STLR_NEEDS_BARRIER
|
||
|
|
bool "Store-Release operations require explicit barriers"
|
||
|
|
def_bool ARCH_MSM8996
|
||
|
|
help
|
||
|
|
Some early samples of MSMTHULIUM SoCs require that an explicit barrier
|
||
|
|
be executed prior to any Store-Release operation (STLR) to comform to
|
||
|
|
ARM memory ordering requirements. If you are building the kernel to
|
||
|
|
work on one of these early designs, select 'Y' here.
|
||
|
|
|
||
|
|
For production kernels, you should say 'N' here.
|
||
|
|
|
||
|
|
config ARM64_SEV_IN_LOCK_UNLOCK
|
||
|
|
bool "Add explicit SEV in the spinlock unlock code path:
|
||
|
|
def_bool ARCH_MSM8996
|
||
|
|
help
|
||
|
|
In certain unexplained cases, the stlr alone might not wakeup
|
||
|
|
the processor waiting in WFE on a spinlock.
|
||
|
|
Add an explicity dsb and SEV in write_unlock, read_unlock
|
||
|
|
and spin_unlock to ensure that the core waiting on the lock
|
||
|
|
wakes up from WFE.
|
||
|
|
|
||
|
|
config SMP
|
||
|
|
bool "Symmetric Multi-Processing"
|
||
|
|
help
|
||
|
|
This enables support for systems with more than one CPU. If
|
||
|
|
you say N here, the kernel will run on single and
|
||
|
|
multiprocessor machines, but will use only one CPU of a
|
||
|
|
multiprocessor machine. If you say Y here, the kernel will run
|
||
|
|
on many, but not all, single processor machines. On a single
|
||
|
|
processor machine, the kernel will run faster if you say N
|
||
|
|
here.
|
||
|
|
|
||
|
|
If you don't know what to do here, say N.
|
||
|
|
|
||
|
|
config SCHED_MC
|
||
|
|
bool "Multi-core scheduler support"
|
||
|
|
depends on SMP
|
||
|
|
help
|
||
|
|
Multi-core scheduler support improves the CPU scheduler's decision
|
||
|
|
making when dealing with multi-core CPU chips at a cost of slightly
|
||
|
|
increased overhead in some places. If unsure say N here.
|
||
|
|
|
||
|
|
config SCHED_SMT
|
||
|
|
bool "SMT scheduler support"
|
||
|
|
depends on SMP
|
||
|
|
help
|
||
|
|
Improves the CPU scheduler's decision making when dealing with
|
||
|
|
MultiThreading at a cost of slightly increased overhead in some
|
||
|
|
places. If unsure say N here.
|
||
|
|
|
||
|
|
config SCHED_MC
|
||
|
|
bool "Multi-core scheduler support"
|
||
|
|
depends on ARM_CPU_TOPOLOGY
|
||
|
|
help
|
||
|
|
Multi-core scheduler support improves the CPU scheduler's decision
|
||
|
|
making when dealing with multi-core CPU chips at a cost of slightly
|
||
|
|
increased overhead in some places. If unsure say N here.
|
||
|
|
|
||
|
|
config SCHED_SMT
|
||
|
|
bool "SMT scheduler support"
|
||
|
|
depends on ARM_CPU_TOPOLOGY
|
||
|
|
help
|
||
|
|
Improves the CPU scheduler's decision making when dealing with
|
||
|
|
MultiThreading at a cost of slightly increased overhead in some
|
||
|
|
places. If unsure say N here.
|
||
|
|
|
||
|
|
config NR_CPUS
|
||
|
|
int "Maximum number of CPUs (2-64)"
|
||
|
|
range 2 64
|
||
|
|
depends on SMP
|
||
|
|
# These have to remain sorted largest to smallest
|
||
|
|
default "8"
|
||
|
|
|
||
|
|
config HOTPLUG_CPU
|
||
|
|
bool "Support for hot-pluggable CPUs"
|
||
|
|
depends on SMP
|
||
|
|
help
|
||
|
|
Say Y here to experiment with turning CPUs off and on. CPUs
|
||
|
|
can be controlled through /sys/devices/system/cpu.
|
||
|
|
|
||
|
|
# The GPIO number here must be sorted by descending number. In case of
|
||
|
|
# a multiplatform kernel, we just want the highest value required by the
|
||
|
|
# selected platforms.
|
||
|
|
config ARCH_NR_GPIO
|
||
|
|
int
|
||
|
|
default 1024 if ARCH_TEGRA
|
||
|
|
default 1024 if ARCH_MSM
|
||
|
|
default 256
|
||
|
|
help
|
||
|
|
Maximum number of GPIOs in the system.
|
||
|
|
|
||
|
|
If unsure, leave the default value.
|
||
|
|
|
||
|
|
|
||
|
|
source kernel/Kconfig.preempt
|
||
|
|
|
||
|
|
config HZ
|
||
|
|
int
|
||
|
|
default 100
|
||
|
|
|
||
|
|
config ARCH_HAS_HOLES_MEMORYMODEL
|
||
|
|
def_bool y if SPARSEMEM
|
||
|
|
|
||
|
|
config ARCH_SPARSEMEM_ENABLE
|
||
|
|
def_bool y
|
||
|
|
select SPARSEMEM_VMEMMAP_ENABLE
|
||
|
|
|
||
|
|
config ARCH_SPARSEMEM_DEFAULT
|
||
|
|
def_bool ARCH_SPARSEMEM_ENABLE
|
||
|
|
|
||
|
|
config ARCH_SELECT_MEMORY_MODEL
|
||
|
|
def_bool ARCH_SPARSEMEM_ENABLE
|
||
|
|
|
||
|
|
config HAVE_ARCH_PFN_VALID
|
||
|
|
def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
|
||
|
|
|
||
|
|
config HW_PERF_EVENTS
|
||
|
|
bool "Enable hardware performance counter support for perf events"
|
||
|
|
depends on PERF_EVENTS
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
Enable hardware performance counter support for perf events. If
|
||
|
|
disabled, perf events will use software events only.
|
||
|
|
|
||
|
|
config PERF_EVENTS_USERMODE
|
||
|
|
bool "Enable usermode access for perf events"
|
||
|
|
depends on PERF_EVENTS
|
||
|
|
help
|
||
|
|
Enable user-mode access to performance counters for perf events.
|
||
|
|
If enabled, the access permissions allowing CPU performance
|
||
|
|
counters to be accessed from user-mode are set.
|
||
|
|
|
||
|
|
If you want user-mode programs to access perf events, say Y
|
||
|
|
|
||
|
|
config PERF_EVENTS_RESET_PMU_DEBUGFS
|
||
|
|
bool "Reset PMU via debugfs node"
|
||
|
|
depends on PERF_EVENTS
|
||
|
|
help
|
||
|
|
Enable the debugfs node that can be used to reset PMUs and all
|
||
|
|
state variables associated with PMUs. If enabled, PMU and internal
|
||
|
|
state variable are cleared.
|
||
|
|
If you want to reset PMU and PMU related internal Perf variables
|
||
|
|
via debugfs then say Y.
|
||
|
|
|
||
|
|
config ARM64_REG_REBALANCE_ON_CTX_SW
|
||
|
|
bool "Rebalance registers during context switches."
|
||
|
|
def_bool ARCH_MSM8996
|
||
|
|
help
|
||
|
|
Forcefully re-balance register rename pools on context switches for
|
||
|
|
improved performance on some devices.
|
||
|
|
|
||
|
|
config SYS_SUPPORTS_HUGETLBFS
|
||
|
|
def_bool y
|
||
|
|
|
||
|
|
config ARCH_WANT_GENERAL_HUGETLB
|
||
|
|
def_bool y
|
||
|
|
|
||
|
|
config ARCH_WANT_HUGE_PMD_SHARE
|
||
|
|
def_bool y if !ARM64_64K_PAGES
|
||
|
|
|
||
|
|
config HAVE_ARCH_TRANSPARENT_HUGEPAGE
|
||
|
|
def_bool y
|
||
|
|
|
||
|
|
config ARCH_HAS_CACHE_LINE_SIZE
|
||
|
|
def_bool y
|
||
|
|
|
||
|
|
source "mm/Kconfig"
|
||
|
|
|
||
|
|
config SECCOMP
|
||
|
|
bool "Enable seccomp to safely compute untrusted bytecode"
|
||
|
|
---help---
|
||
|
|
This kernel feature is useful for number crunching applications
|
||
|
|
that may need to compute untrusted bytecode during their
|
||
|
|
execution. By using pipes or other transports made available to
|
||
|
|
the process as file descriptors supporting the read/write
|
||
|
|
syscalls, it's possible to isolate those applications in
|
||
|
|
their own address space using seccomp. Once seccomp is
|
||
|
|
enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
|
||
|
|
and the task is only allowed to execute a few safe syscalls
|
||
|
|
defined by each seccomp mode.
|
||
|
|
|
||
|
|
config XEN_DOM0
|
||
|
|
def_bool y
|
||
|
|
depends on XEN
|
||
|
|
|
||
|
|
config XEN
|
||
|
|
bool "Xen guest support on ARM64"
|
||
|
|
depends on ARM64 && OF
|
||
|
|
select SWIOTLB_XEN
|
||
|
|
help
|
||
|
|
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
|
||
|
|
|
||
|
|
config FORCE_MAX_ZONEORDER
|
||
|
|
int
|
||
|
|
default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
|
||
|
|
default "11"
|
||
|
|
|
||
|
|
menuconfig ARMV8_DEPRECATED
|
||
|
|
bool "Emulate deprecated/obsolete ARMv8 instructions"
|
||
|
|
depends on COMPAT
|
||
|
|
help
|
||
|
|
Legacy software support may require certain instructions
|
||
|
|
that have been deprecated or obsoleted in the architecture.
|
||
|
|
|
||
|
|
Enable this config to enable selective emulation of these
|
||
|
|
features.
|
||
|
|
|
||
|
|
If unsure, say Y
|
||
|
|
|
||
|
|
if ARMV8_DEPRECATED
|
||
|
|
|
||
|
|
config SWP_EMULATION
|
||
|
|
bool "Emulate SWP/SWPB instructions"
|
||
|
|
help
|
||
|
|
ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
|
||
|
|
they are always undefined. Say Y here to enable software
|
||
|
|
emulation of these instructions for userspace using LDXR/STXR.
|
||
|
|
|
||
|
|
In some older versions of glibc [<=2.8] SWP is used during futex
|
||
|
|
trylock() operations with the assumption that the code will not
|
||
|
|
be preempted. This invalid assumption may be more likely to fail
|
||
|
|
with SWP emulation enabled, leading to deadlock of the user
|
||
|
|
application.
|
||
|
|
|
||
|
|
NOTE: when accessing uncached shared regions, LDXR/STXR rely
|
||
|
|
on an external transaction monitoring block called a global
|
||
|
|
monitor to maintain update atomicity. If your system does not
|
||
|
|
implement a global monitor, this option can cause programs that
|
||
|
|
perform SWP operations to uncached memory to deadlock.
|
||
|
|
|
||
|
|
If unsure, say Y
|
||
|
|
|
||
|
|
config CP15_BARRIER_EMULATION
|
||
|
|
bool "Emulate CP15 Barrier instructions"
|
||
|
|
help
|
||
|
|
The CP15 barrier instructions - CP15ISB, CP15DSB, and
|
||
|
|
CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
|
||
|
|
strongly recommended to use the ISB, DSB, and DMB
|
||
|
|
instructions instead.
|
||
|
|
|
||
|
|
Say Y here to enable software emulation of these
|
||
|
|
instructions for AArch32 userspace code. When this option is
|
||
|
|
enabled, CP15 barrier usage is traced which can help
|
||
|
|
identify software that needs updating.
|
||
|
|
|
||
|
|
If unsure, say Y
|
||
|
|
|
||
|
|
config SETEND_EMULATION
|
||
|
|
bool "Emulate SETEND instruction"
|
||
|
|
help
|
||
|
|
The SETEND instruction alters the data-endianness of the
|
||
|
|
AArch32 EL0, and is deprecated in ARMv8.
|
||
|
|
|
||
|
|
Say Y here to enable software emulation of the instruction
|
||
|
|
for AArch32 userspace code.
|
||
|
|
|
||
|
|
Note: All the cpus on the system must have mixed endian support at EL0
|
||
|
|
for this feature to be enabled. If a new CPU - which doesn't support mixed
|
||
|
|
endian - is hotplugged in after this feature has been enabled, there could
|
||
|
|
be unexpected results in the applications.
|
||
|
|
|
||
|
|
If unsure, say Y
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
menu "Boot options"
|
||
|
|
|
||
|
|
config CMDLINE
|
||
|
|
string "Default kernel command string"
|
||
|
|
default ""
|
||
|
|
help
|
||
|
|
Provide a set of default command-line options at build time by
|
||
|
|
entering them here. As a minimum, you should specify the the
|
||
|
|
root device (e.g. root=/dev/nfs).
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "Kernel command line type" if CMDLINE != ""
|
||
|
|
default CMDLINE_FROM_BOOTLOADER
|
||
|
|
|
||
|
|
config CMDLINE_FROM_BOOTLOADER
|
||
|
|
bool "Use bootloader kernel arguments if available"
|
||
|
|
help
|
||
|
|
Uses the command-line options passed by the boot loader. If
|
||
|
|
the boot loader doesn't provide any, the default kernel command
|
||
|
|
string provided in CMDLINE will be used.
|
||
|
|
|
||
|
|
config CMDLINE_EXTEND
|
||
|
|
bool "Extend bootloader kernel arguments"
|
||
|
|
help
|
||
|
|
The command-line arguments provided by the boot loader will be
|
||
|
|
appended to the default kernel command string.
|
||
|
|
|
||
|
|
config CMDLINE_FORCE
|
||
|
|
bool "Always use the default kernel command string"
|
||
|
|
help
|
||
|
|
Always use the default kernel command string, even if the boot
|
||
|
|
loader passes other arguments to the kernel.
|
||
|
|
This is useful if you cannot or don't want to change the
|
||
|
|
command-line options your boot loader passes to the kernel.
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
config EFI_STUB
|
||
|
|
bool
|
||
|
|
|
||
|
|
config EFI
|
||
|
|
bool "UEFI runtime support"
|
||
|
|
depends on OF && !CPU_BIG_ENDIAN
|
||
|
|
select LIBFDT
|
||
|
|
select UCS2_STRING
|
||
|
|
select EFI_PARAMS_FROM_FDT
|
||
|
|
select EFI_RUNTIME_WRAPPERS
|
||
|
|
select EFI_STUB
|
||
|
|
select EFI_ARMSTUB
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This option provides support for runtime services provided
|
||
|
|
by UEFI firmware (such as non-volatile variables, realtime
|
||
|
|
clock, and platform reset). A UEFI stub is also provided to
|
||
|
|
allow the kernel to be booted as an EFI application. This
|
||
|
|
is only useful on systems that have UEFI firmware.
|
||
|
|
|
||
|
|
config BUILD_ARM64_APPENDED_DTB_IMAGE
|
||
|
|
bool "Build a concatenated Image.gz/dtb by default"
|
||
|
|
depends on OF
|
||
|
|
help
|
||
|
|
Enabling this option will cause a concatenated Image.gz and list of
|
||
|
|
DTBs to be built by default (instead of a standalone Image.gz.)
|
||
|
|
The image will built in arch/arm64/boot/Image.gz-dtb
|
||
|
|
|
||
|
|
config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
|
||
|
|
string "Default dtb names"
|
||
|
|
depends on BUILD_ARM64_APPENDED_DTB_IMAGE
|
||
|
|
help
|
||
|
|
Space separated list of names of dtbs to append when
|
||
|
|
building a concatenated Image.gz-dtb.
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
menu "Userspace binary formats"
|
||
|
|
|
||
|
|
source "fs/Kconfig.binfmt"
|
||
|
|
|
||
|
|
config COMPAT
|
||
|
|
bool "Kernel support for 32-bit EL0"
|
||
|
|
depends on !ARM64_64K_PAGES
|
||
|
|
select COMPAT_BINFMT_ELF
|
||
|
|
select HAVE_UID16
|
||
|
|
select OLD_SIGSUSPEND3
|
||
|
|
select COMPAT_OLD_SIGACTION
|
||
|
|
help
|
||
|
|
This option enables support for a 32-bit EL0 running under a 64-bit
|
||
|
|
kernel at EL1. AArch32-specific components such as system calls,
|
||
|
|
the user helper functions, VFP support and the ptrace interface are
|
||
|
|
handled appropriately by the kernel.
|
||
|
|
|
||
|
|
If you want to execute 32-bit userspace applications, say Y.
|
||
|
|
|
||
|
|
config SYSVIPC_COMPAT
|
||
|
|
def_bool y
|
||
|
|
depends on COMPAT && SYSVIPC
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
menu "Power management options"
|
||
|
|
|
||
|
|
source "kernel/power/Kconfig"
|
||
|
|
|
||
|
|
config ARCH_SUSPEND_POSSIBLE
|
||
|
|
def_bool y
|
||
|
|
|
||
|
|
config ARM64_CPU_SUSPEND
|
||
|
|
def_bool PM_SLEEP
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
menu "CPU Power Management"
|
||
|
|
|
||
|
|
source "drivers/cpuidle/Kconfig"
|
||
|
|
|
||
|
|
source "drivers/cpufreq/Kconfig"
|
||
|
|
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
#
|
||
|
|
# BEGIN RKP_CFP CONFIG OPTIONS
|
||
|
|
#
|
||
|
|
|
||
|
|
menu "Control Flow Protection"
|
||
|
|
|
||
|
|
config RKP_CFP
|
||
|
|
bool "Hyperdrive ROP protection"
|
||
|
|
# depends on TIMA_RKP
|
||
|
|
# Disable RKP for now, keep getting TIMA_RKP_VMM_PANIC when doing sleep.S code for saving/restoring x17.
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Static binary instrumentation of direct/indirect branches to prevent
|
||
|
|
return-oriented programming (ROP) attacks and jump-oriented programming (JOP) attacks.
|
||
|
|
|
||
|
|
config RKP_CFP_ROPP
|
||
|
|
bool "Hyperdrive: encrypt return-addresses"
|
||
|
|
select RKP_CFP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
XOR return-addresses with the reserved key register on call/return from functions
|
||
|
|
to encrypt/decrypt return-addresses before they are pushed onto the stack.
|
||
|
|
Also, save the key during context-switches and suspend/resume cycles.
|
||
|
|
|
||
|
|
choice
|
||
|
|
prompt "ROPP key"
|
||
|
|
default RKP_CFP_ROPP_RANDOM_KEY
|
||
|
|
depends on RKP_CFP && RKP_CFP_ROPP
|
||
|
|
help
|
||
|
|
ROPP key configuration
|
||
|
|
|
||
|
|
config RKP_CFP_ROPP_HYPKEY
|
||
|
|
bool "Use hypervisor for key secure storage"
|
||
|
|
help
|
||
|
|
if n, use random key or zero key
|
||
|
|
|
||
|
|
config RKP_CFP_ROPP_RANDOM_KEY
|
||
|
|
bool "Hyperdrive: use pseudo random key for return-address encryption"
|
||
|
|
help
|
||
|
|
if n, use hyp key or zero key
|
||
|
|
|
||
|
|
config RKP_CFP_ROPP_ZERO_KEY
|
||
|
|
bool "Hyperdrive: use zero key for return-address encryption"
|
||
|
|
help
|
||
|
|
if n, use hyp key or random key
|
||
|
|
endchoice
|
||
|
|
|
||
|
|
config RKP_CFP_JOPP
|
||
|
|
bool "Just to function entry only, Restrict BLR jump target to a valid function entry point and no br in C code"
|
||
|
|
select RKP_CFP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
We need nop spacers above ever potential target of a blr jump instruction.
|
||
|
|
The compiler already adds spacers for C functions.
|
||
|
|
We need to define a VECTOR_ENTRY macro for exception vector definitions. We don't
|
||
|
|
want to add nops to exception vectors, since they need PRECISE alignment. Need to
|
||
|
|
put FALLTHROUGH for ASM fall through
|
||
|
|
|
||
|
|
No BR in C code requires to disable BPF, as it has a lot of jump, which can be used
|
||
|
|
as dispatch gadget for JOPP
|
||
|
|
|
||
|
|
|
||
|
|
config RKP_CFP_JOPP_MAGIC
|
||
|
|
hex "Magic number put just above function labels to restrict BLR to function entry points"
|
||
|
|
# depends on RKP_CFP && RKP_CFP_JOPP
|
||
|
|
# basically it depends on above line but it's needed for avoiding a build break
|
||
|
|
default "0xb3ea3bad"
|
||
|
|
|
||
|
|
config RKP_CFP_FIX_SMC_BUG
|
||
|
|
bool "Hyperdrive: [INSECURE] hack broken smc calls to save/restore RRK after it clobbers it"
|
||
|
|
depends on RKP_CFP_ROPP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
As of bootloader version "G920VVRE1BOE4" of the TrustZone for exynos7420, the smc
|
||
|
|
instruction sets register x17 to zero. Too bad for us, we store our key there! In
|
||
|
|
the meantime, save x17 (and other reserved registers) before making the call.
|
||
|
|
|
||
|
|
To reproduce this bug, disable this option and set a JTAG breakpoint at
|
||
|
|
exynos_smc_readsfr which gets called during early boot (start_kernel). Watch x17
|
||
|
|
get zeroed after the smc call returns.
|
||
|
|
|
||
|
|
ADDITIONAL BUG BECAUSE OF THIS:
|
||
|
|
If we take an interrupt at the instruction IMMEDIATELY after "smc #0", we won't be
|
||
|
|
able to restore x17 to the key before entering el1_irq. To work around this, we
|
||
|
|
reload the key in kernel_entry.
|
||
|
|
endmenu
|
||
|
|
|
||
|
|
#
|
||
|
|
# END RKP_CFP CONFIG OPTIONS
|
||
|
|
#
|
||
|
|
|
||
|
|
config DRV_SAMSUNG
|
||
|
|
bool "samsung device dedicated drivers option"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This is driver option for samsung sec_class
|
||
|
|
Say y here to enable samsung classes for drivers
|
||
|
|
Provide option of enabling sec class
|
||
|
|
Supports sec drivers key, touch, sec_debug etc
|
||
|
|
|
||
|
|
config RTC_AUTO_PWRON
|
||
|
|
bool "RTC Auto Power on PM8994 PMICs"
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Support for the auto power on alarm on the PM8994 PMIC.
|
||
|
|
Say Y if you want to enable this feature.
|
||
|
|
|
||
|
|
config RTC_AUTO_PWRON_PARAM
|
||
|
|
bool "RTC Auto Power on with param PM8994 PMICs"
|
||
|
|
depends on RTC_AUTO_PWRON
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
This option is used to prevent invalid RTC alarm power on.
|
||
|
|
Say Y if you want to enable this feature.
|
||
|
|
|
||
|
|
config BT_BCM4359
|
||
|
|
bool "Enable BCM4359 driver"
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Adds BCM4358 RFKILL driver for Broadcom BCM4359 chipset. default is n.
|
||
|
|
|
||
|
|
config BT_BLUESLEEP
|
||
|
|
bool "Enable BlUESLEEP driver"
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Adds BlUESLEEP driver for Broadcom chipset. default is n.
|
||
|
|
|
||
|
|
config RELOCATABLE_KERNEL
|
||
|
|
bool "set kernel to relocatable in both virtual and physical address"
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This configuare will allow you to config the kernel into position independent kernel, with '--PIE' insert into LD script.
|
||
|
|
|
||
|
|
config TIMA_RKP
|
||
|
|
bool "Samsung KNOX realtime kernel protection"
|
||
|
|
depends on TIMA
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
this enables realtime kernel protection
|
||
|
|
|
||
|
|
config RKP_KDP
|
||
|
|
bool "Protection for cred structure"
|
||
|
|
depends on TIMA_RKP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Prevents unauthorized cred modification.
|
||
|
|
|
||
|
|
config RKP_NS_PROT
|
||
|
|
bool "Protection for cred structure"
|
||
|
|
depends on RKP_KDP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Prevents unauthorized cred modification.
|
||
|
|
|
||
|
|
|
||
|
|
config RKP_DMAP_PROT
|
||
|
|
bool "Page Double Mapping protection"
|
||
|
|
depends on RKP_KDP
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
Prevents unauthorized mapping for page table.
|
||
|
|
|
||
|
|
config BARCODE_PAINTER
|
||
|
|
bool "Bootloader Barcode Print MSM8996"
|
||
|
|
depends on ARCH_MSM8996
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
This option is used to add Barcode Print Func.
|
||
|
|
Say Y if you want to enable this feature.
|
||
|
|
|
||
|
|
config USER_RESET_DEBUG
|
||
|
|
bool "reset reason debug feature in user version"
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
This option provides reset history log in user version.
|
||
|
|
This option enable proc/reset_reason support
|
||
|
|
|
||
|
|
config SEC_PERIPHERAL_SECURE_CHK
|
||
|
|
bool "PERIPHERAL SECURE check"
|
||
|
|
default n
|
||
|
|
help
|
||
|
|
To check the authentication of peripheral image.
|
||
|
|
|
||
|
|
source "net/Kconfig"
|
||
|
|
|
||
|
|
source "drivers/Kconfig"
|
||
|
|
|
||
|
|
source "drivers/firmware/Kconfig"
|
||
|
|
|
||
|
|
source "fs/Kconfig"
|
||
|
|
|
||
|
|
source "arch/arm64/kvm/Kconfig"
|
||
|
|
|
||
|
|
source "arch/arm64/Kconfig.debug"
|
||
|
|
|
||
|
|
source "security/Kconfig"
|
||
|
|
|
||
|
|
source "crypto/Kconfig"
|
||
|
|
if CRYPTO
|
||
|
|
source "arch/arm64/crypto/Kconfig"
|
||
|
|
endif
|
||
|
|
|
||
|
|
source "lib/Kconfig"
|
||
|
|
|
||
|
|
source "arch/arm64/mm/Kconfig"
|