/* * Copyright (c) 2015, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include "skeleton.dtsi" #include #include #include / { model = "Qualcomm Technologies, Inc. MDM FERMIUM"; compatible = "qcom,mdmfermium"; qcom,msm-id = <290 0x10000>, <296 0x10000>, <297 0x10000>, <298 0x10000>, <299 0x10000>; interrupt-parent = <&intc>; aliases { qpic_nand1 = &qnand_1; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; modem_adsp_mem: modem_adsp_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x82a00000 0x5000000>; }; cnss_debug_mem: cnss_debug_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x87a00000 0x200000>; }; external_image_mem: external_image_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x87c00000 0x400000>; }; audio_mem: audio_region@0 { compatible = "shared-dma-pool"; reusable; alignment = <0x400000>; size = <0x400000>; }; }; aliases { /* smdtty devices */ smd7 = &smdtty_data1; smd8 = &smdtty_data4; smd11 = &smdtty_data11; smd21 = &smdtty_data21; smd36 = &smdtty_loopback; /* spi device */ spi1 = &spi_1; i2c4 = &i2c_4; }; cpus { #size-cells = <0>; #address-cells = <1>; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; qcom,limits-info = <&mitigation_profile0>; }; }; soc: soc { }; }; #include "mdmfermium-ion.dtsi" #include "mdmfermium-smp2p.dtsi" #include "mdmfermium-bus.dtsi" #include "mdmfermium-coresight.dtsi" #include "mdmfermium-pm.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; ranges; intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; }; qcom,mpm2-sleep-counter@4a3000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0x4a3000 0x1000>; clock-frequency = <32768>; }; timer@b020000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0xb020000 0x1000>; clock-frequency = <19200000>; frame@b021000 { frame-number = <0>; interrupts = <0 7 0x4>, <0 6 0x4>; reg = <0xb021000 0x1000>, <0xb022000 0x1000>; }; frame@b023000 { frame-number = <1>; interrupts = <0 8 0x4>; reg = <0xb023000 0x1000>; status = "disabled"; }; frame@b024000 { frame-number = <2>; interrupts = <0 9 0x4>; reg = <0xb024000 0x1000>; status = "disabled"; }; frame@b025000 { frame-number = <3>; interrupts = <0 10 0x4>; reg = <0xb025000 0x1000>; status = "disabled"; }; frame@b026000 { frame-number = <4>; interrupts = <0 11 0x4>; reg = <0xb026000 0x1000>; status = "disabled"; }; frame@b027000 { frame-number = <5>; interrupts = <0 12 0x4>; reg = <0xb027000 0x1000>; status = "disabled"; }; frame@b028000 { frame-number = <6>; interrupts = <0 13 0x4>; reg = <0xb028000 0x1000>; status = "disabled"; }; frame@b029000 { frame-number = <7>; interrupts = <0 14 0x4>; reg = <0xb029000 0x1000>; status = "disabled"; }; }; qcom,wdt@b017000 { compatible = "qcom,msm-watchdog"; reg = <0xb017000 0x1000>; reg-names = "wdt-base"; interrupts = <0 3 0>, <0 4 0>; qcom,bark-time = <11000>; qcom,pet-time = <10000>; }; qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x10000>; /* 64K EBI1 buffer */ }; qcom,msm-imem@8600000 { compatible = "qcom,msm-imem"; reg = <0x08600000 0x1000>; /* Address and size of IMEM */ ranges = <0x0 0x08600000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 8>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 32>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 200>; }; }; restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>, <0x193d100 0x4>; reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; jtag_fuse: jtagfuse@a601c { compatible = "qcom,jtag-fuse-v2"; reg = <0xa601c 0x8>; reg-names = "fuse-base"; }; jtag_mm: jtagmm@6042000 { compatible = "qcom,jtagv8-mm"; reg = <0x6042000 0x1000>, <0x6040000 0x1000>; reg-names = "etm-base", "debug-base"; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; qcom,coresight-jtagmm-cpu = <&CPU0>; }; clock_gcc: qcom,gcc@1800000 { compatible = "qcom,gcc-mdmfermium"; reg = <0x1800000 0x80000>, <0x0b008000 0x00050>; reg-names = "cc_base", "apcs_base"; vdd_dig-supply = <&mdmfermium_s3_level>; vdd_stromer_dig-supply = <&mdmfermium_s3_level_ao>; #clock-cells = <1>; }; clock_debug: qcom,debug@1874000 { compatible = "qcom,cc-debug-mdmfermium"; reg = <0x1800000 0x80000>, <0xb01101c 0x8>; reg-names = "cc_base", "meas"; #clock-cells = <1>; }; clock_cpu: qcom,clock-a7@0b010008 { compatible = "qcom,clock-a7-mdmfermium"; reg = <0x0b010008 0x8>, <0x000a412c 0x8>; reg-names = "rcg-base", "efuse"; qcom,safe-freq = < 400000000 >; cpu-vdd-supply = <&apc_vreg_corner>; qcom,enable-opp; clocks = <&clock_gcc clk_gpll0_ao_clk_src>, <&clock_gcc clk_a7sspll>; clock-names = "clk-1", "clk-5"; qcom,speed0-bin-v0 = < 0 0>, < 400000000 1>, < 800000000 2>, < 1305600000 7>; #clock-cells = <1>; }; cpubw: qcom,cpubw { compatible = "qcom,devbw"; governor = "cpufreq"; qcom,src-dst-ports = <1 512>; qcom,active-only; qcom,bw-tbl = < 366 /* 48 MHz */>, < 732 /* 96 MHz */>, < 952 /* 124.8 MHz */>, < 1171 /* 153.6 MHz */>, < 1831 /* 240 MHz */>, < 2343 /* 307.2 MHZ */>; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 400000 732>, < 800000 1171>, < 998400 1831>, < 1094400 2343>, < 1305600 2343>; }; }; qcom,cpu-bwmon { compatible = "qcom,bimc-bwmon2"; reg = <0x408000 0x300>, <0x401000 0x200>; reg-names = "base", "global_base"; interrupts = <0 183 4>; qcom,mport = <0>; qcom,target-dev = <&cpubw>; }; qcom,msm-cpufreq { reg = <0 4>; compatible = "qcom,msm-cpufreq"; clocks = <&clock_cpu clk_a7ssmux>; clock-names = "cpu0_clk"; qcom,cpufreq-table = < 400000 >, < 800000 >, < 998400 >, < 1094400 >, < 1190400 >, < 1248000 >, < 1305600 >; }; qcom,sps { compatible = "qcom,msm_sps_4k"; qcom,pipe-attr-ee; }; blsp1_uart5: serial@78b3000 { /* BLSP1 UART5 */ compatible = "qcom,msm-lsuart-v14"; reg = <0x78b3000 0x200>; interrupts = <0 121 0>; clocks = <&clock_gcc clk_gcc_blsp1_uart5_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; status = "disabled"; }; dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0x7884000 0x2b000>; interrupts = <0 238 0>; qcom,summing-threshold = <10>; }; i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b8000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 98 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 18 64 0x20000020 0x20>, <&dma_blsp1 19 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; blsp1_uart3: uart@78b1000 { compatible = "qcom,msm-hsuart-v14"; reg = <0x78b1000 0x200>, <0x7884000 0x2b000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 119 0 1 &intc 0 238 0 2 &tlmm_pinmux 1 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <4>; qcom,bam-rx-ep-pipe-index = <5>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_sleep>; pinctrl-1 = <&blsp1_uart3_active>; qcom,msm-bus,name = "blsp1_uart3"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; usb_otg: usb@78d9000 { compatible = "qcom,hsusb-otg"; reg = <0x78d9000 0x400>, <0x6c000 0x200>; reg-names = "core", "phy_csr"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 134 0>,<0 139 0>; interrupt-names = "core_irq", "async_irq"; hsusb_vdd_dig-supply = <&mdmfermium_l9>; HSUSB_1p8-supply = <&mdmfermium_l2>; HSUSB_3p3-supply = <&mdmfermium_l4>; qcom,vdd-voltage-level = <0 1225000 1225000>; qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ qcom,hsusb-otg-mode = <3>; /* OTG mode */ qcom,hsusb-otg-otg-control = <2>; /* PMIC control */ qcom,usbid-gpio = <&pm8019_mpps 1 0>; qcom,hsusb-log2-itc = <4>; qcom,dp-manual-pullup; qcom,boost-sysclk-with-streaming; qcom,phy-dvdd-always-on; qcom,hsusb-otg-lpm-on-dev-suspend; qcom,axi-prefetch-enable; qcom,hsusb-otg-mpm-dpsehv-int = <49>; qcom,hsusb-otg-mpm-dmsehv-int = <58>; qcom,hsusb-otg-delay-lpm; qcom,msm-bus,name = "usb2"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <87 512 0 0>, <87 512 80000 0>, <87 512 6000 6000>; clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>, <&clock_gcc clk_gcc_usb_hs_system_clk>, <&clock_gcc clk_gcc_usb2a_phy_sleep_clk>, <&clock_gcc clk_bimc_usb_a_clk>, <&clock_gcc clk_pcnoc_usb_a_clk>, <&clock_gcc clk_gcc_qusb2_phy_clk>, <&clock_gcc clk_gcc_usb2_hs_phy_only_clk>, <&clock_gcc clk_gcc_usb_hs_phy_cfg_ahb_clk>, <&clock_gcc clk_xo_otg_clk>; clock-names = "iface_clk", "core_clk", "sleep_clk", "bimc_clk", "pcnoc_clk", "phy_reset_clk", "phy_por_clk", "phy_csr_clk", "xo"; qcom,bus-clk-rate = <240000000 0 100000000>; qcom,max-nominal-sysclk-rate = <133330000>; qcom,usbbam@78c4000 { compatible = "qcom,usb-bam-msm"; reg = <0x78c4000 0x15000>; interrupt-parent = <&intc>; interrupts = <0 135 0>; qcom,bam-type = <1>; qcom,usb-bam-num-pipes = <2>; qcom,usb-bam-fifo-baseaddr = <0x08603800>; qcom,ignore-core-reset-ack; qcom,disable-clk-gating; qcom,reset-bam-on-disconnect; qcom,pipe0 { label = "hsusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x6084000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0x600>; qcom,descriptor-fifo-offset = <0x600>; qcom,descriptor-fifo-size = <0x200>; }; }; }; android_usb: android_usb@086000c8 { compatible = "qcom,android-usb"; reg = <0x086000c8 0xc8>; qcom,pm-qos-latency = <2 1001 12701>; }; qnand_1: nand@7980000 { compatible = "qcom,msm-nand"; reg = <0x07980000 0x1000>, <0x07984000 0x1a000>; reg-names = "nand_phys", "bam_phys"; interrupts = <0 132 0>; interrupt-names = "bam_irq"; qcom,msm-bus,name = "qpic_nand"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <91 512 0 0>, /* Voting for max b/w on PNOC bus for now */ <91 512 400000 800000>; clock-names = "core_clk"; clocks = <&clock_gcc clk_qpic_clk>; status = "disabled"; }; tsens: tsens@4a8000 { compatible = "qcom,mdmfermium-tsens"; reg = <0x4a8000 0x2000>, <0xa4000 0x1000>; reg-names = "tsens_physical", "tsens_eeprom_physical"; interrupts = <0 184 0>; interrupt-names = "tsens-upper-lower"; qcom,sensors = <5>; qcom,slope = <3000 3000 3000 3000 3000>; qcom,sensor-id = <0 1 2 3 4>; }; qcom,msm-thermal { compatible = "qcom,msm-thermal"; qcom,sensor-id = <4>; qcom,poll-ms = <250>; qcom,limit-temp = <60>; qcom,temp-hysteresis = <10>; qcom,freq-step = <2>; qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; vdd-dig-supply = <&mdmfermium_s3_floor_level>; qcom,vdd-dig-rstr{ qcom,vdd-rstr-reg = "vdd-dig"; qcom,levels = ; qcom,min-level = ; }; }; qcom,sensor-information { compatible = "qcom,sensor-information"; sensor_information0: qcom,sensor-information-0 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor0"; }; sensor_information1: qcom,sensor-information-1 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor1"; }; sensor_information2: qcom,sensor-information-2 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor2"; }; sensor_information3: qcom,sensor-information-3 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor3"; }; sensor_information4: qcom,sensor-information-4 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor4"; }; sensor_information5: qcom,sensor-information-5 { qcom,sensor-type = "adc"; qcom,sensor-name = "pa_therm0"; }; sensor_information6: qcom,sensor-information-6 { qcom,sensor-type = "adc"; qcom,sensor-name = "pa_therm1"; }; sensor_information7: qcom,sensor-information-7 { qcom,sensor-type = "adc"; qcom,sensor-name = "xo_therm"; }; sensor_information8: qcom,sensor-information-8 { qcom,sensor-type = "adc"; qcom,sensor-name = "xo_therm_amux"; }; }; mitigation_profile0: qcom,limit_info-0 { qcom,temperature-sensor = <&sensor_information4>; }; qcom,ipc-spinlock@1905000 { compatible = "qcom,ipc-spinlock-sfpb"; reg = <0x1905000 0x8000>; qcom,num-locks = <8>; }; qcom,smem@87d00000 { compatible = "qcom,smem"; reg = <0x87d00000 0x100000>, <0x0b011008 0x4>, <0x60000 0x8000>, <0x193d000 0x8>; reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg"; qcom,mpu-enabled; qcom,smd-modem { compatible = "qcom,smd"; qcom,smd-edge = <0>; qcom,smd-irq-offset = <0x0>; qcom,smd-irq-bitmask = <0x1000>; interrupts = <0 25 1>; label = "modem"; }; qcom,smsm-modem { compatible = "qcom,smsm"; qcom,smsm-edge = <0>; qcom,smsm-irq-offset = <0x0>; qcom,smsm-irq-bitmask = <0x2000>; interrupts = <0 26 1>; }; qcom,smd-rpm { compatible = "qcom,smd"; qcom,smd-edge = <15>; qcom,smd-irq-offset = <0x0>; qcom,smd-irq-bitmask = <0x1>; interrupts = <0 168 1>; label = "rpm"; qcom,irq-no-suspend; qcom,not-loadable; }; }; rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; qcom,smdtty { compatible = "qcom,smdtty"; smdtty_data1: qcom,smdtty-data1 { qcom,smdtty-remote = "modem"; qcom,smdtty-port-name = "DATA1"; }; smdtty_data4: qcom,smdtty-data4 { qcom,smdtty-remote = "modem"; qcom,smdtty-port-name = "DATA4"; }; smdtty_data11: qcom,smdtty-data11 { qcom,smdtty-remote = "modem"; qcom,smdtty-port-name = "DATA11"; }; smdtty_data21: qcom,smdtty-data21 { qcom,smdtty-remote = "modem"; qcom,smdtty-port-name = "DATA21"; }; smdtty_loopback: smdtty-loopback { qcom,smdtty-remote = "modem"; qcom,smdtty-port-name = "LOOPBACK"; qcom,smdtty-dev-name = "LOOPBACK_TTY"; }; }; qcom,smdpkt { compatible = "qcom,smdpkt"; qcom,smdpkt-data5-cntl { qcom,smdpkt-remote = "modem"; qcom,smdpkt-port-name = "DATA5_CNTL"; qcom,smdpkt-dev-name = "smdcntl0"; }; qcom,smdpkt-data22 { qcom,smdpkt-remote = "modem"; qcom,smdpkt-port-name = "DATA22"; qcom,smdpkt-dev-name = "smd22"; }; qcom,smdpkt-data40-cntl { qcom,smdpkt-remote = "modem"; qcom,smdpkt-port-name = "DATA40_CNTL"; qcom,smdpkt-dev-name = "smdcntl8"; }; qcom,smdpkt-apr-apps2 { qcom,smdpkt-remote = "modem"; qcom,smdpkt-port-name = "apr_apps2"; qcom,smdpkt-dev-name = "apr_apps2"; }; qcom,smdpkt-loopback { qcom,smdpkt-remote = "modem"; qcom,smdpkt-port-name = "LOOPBACK"; qcom,smdpkt-dev-name = "smd_pkt_loopback"; }; }; qcom,ipc_router { compatible = "qcom,ipc_router"; qcom,node-id = <1>; }; qcom,ipc_router_modem_xprt { compatible = "qcom,ipc_router_smd_xprt"; qcom,ch-name = "IPCRTR"; qcom,xprt-remote = "modem"; qcom,xprt-linkid = <1>; qcom,xprt-version = <1>; qcom,fragmented-data; }; qcom,bam_dmux@4044000 { compatible = "qcom,bam_dmux"; reg = <0x4044000 0x19000>; interrupts = <0 29 1>; qcom,rx-ring-size = <32>; qcom,max-rx-mtu = <4096>; qcom,fast-shutdown; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, <0x2400000 0x800000>, <0x2c00000 0x800000>, <0x3800000 0x200000>, <0x200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupts = <0 190 0>; qcom,pmic-arb-channel = <0>; qcom,pmic-arb-max-peripherals = <128>; qcom,pmic-arb-max-periph-interrupts = <128>; qcom,pmic-arb-ee = <0>; #interrupt-cells = <3>; interrupt-controller; #address-cells = <1>; #size-cells = <0>; cell-index = <0>; qcom,not-wakeup; /* Needed until MPM is fully configured. */ }; spi_1: spi@78b6000 { /* BLSP1 QUP1 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0x78b6000 0x600>, <0x7884000 0x2b000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 96 0>, <0 238 0>; spi-max-frequency = <19200000>; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi1_default &spi1_cs0_active>; pinctrl-1 = <&spi1_sleep &spi1_cs0_sleep>; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,infinite-mode = <0>; qcom,use-bam; qcom,use-pinctrl; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <14>; qcom,bam-producer-pipe-index = <15>; qcom,master-id = <86>; status = "disabled"; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x04080000 0x100>, <0x0194f000 0x010>, <0x01950000 0x008>, <0x01951000 0x008>, <0x04020000 0x040>, <0x0183e000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; interrupts = <0 24 1>; vdd_cx-supply = <&mdmfermium_s3_level>; vdd_cx-voltage = ; vdd_mx-supply = <&mdmfermium_l12_level>; vdd_mx-uV = ; vdd_pll-supply = <&mdmfermium_l3>; qcom,vdd_pll = <1800000>; clocks = <&clock_gcc clk_xo_pil_mss_clk>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; qcom,proxy-clock-names = "xo"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,qdsp6v56-1-8-inrush-current; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; memory-region = <&modem_adsp_mem>; }; }; #include "mdmfermium-rpm-regulator.dtsi" #include "msm-pm8019.dtsi" #include "mdmfermium-regulator.dtsi" &pm8019_vadc { chan@31 { label = "batt_id_therm"; reg = <0x31>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <0>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; }; chan@33 { label = "pa_therm0"; reg = <0x33>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <2>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; }; chan@34 { label = "pa_therm1"; reg = <0x34>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <2>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; }; chan@32 { label = "xo_therm"; reg = <0x32>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <4>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; }; chan@3c { label = "xo_therm_amux"; reg = <0x3c>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <4>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; }; }; &pm8019_adc_tm { /* Channel Node */ chan@33 { label = "pa_therm0"; reg = <0x33>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <2>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; qcom,btm-channel-number = <0x48>; qcom,thermal-node; }; chan@34 { label = "pa_therm1"; reg = <0x34>; qcom,decimation = <0>; qcom,pre-div-channel-scaling = <0>; qcom,calibration-type = "ratiometric"; qcom,scale-function = <2>; qcom,hw-settle-time = <2>; qcom,fast-avg-setup = <0>; qcom,btm-channel-number = <0x68>; qcom,thermal-node; }; };