/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {

	msm_bus: qcom,kgsl-busmon{
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
	};

	/* Bus governor */
	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		qcom,bw-tbl =
			< 0 >,		/* Off */
			< 146 >,	/* 9.6 MHz */
			< 1525 >,	/* 100.0 MHz */
			< 1977 >,	/* 129.6 MHz */
			< 2929 >,	/* 192.0 MHz */
			< 3955 >,	/* 259.2 MHz */
			< 5346 >,	/* 350.4 MHz */
			< 5712 >,	/* 374.4 MHz */
			< 6152 >,	/* 403.2 MHz */
			< 7031 >;	/* 460.8 MHz */
	};

	qcom,gpu-bwmon@410000 {
		compatible = "qcom,bimc-bwmon";
		reg = <0x00410000 0x300>, <0x00401000 0x200>;
		reg-names = "base", "global_base";
		interrupts = <0 183 4>;
		qcom,mport = <2>;
		qcom,target-dev = <&gpubw>;
	};

	msm_gpu: qcom,kgsl-3d0@1c00000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		reg = <0x1c00000 0x10000
		       0x1c20000 0x10000>;
		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
		interrupts = <0 33 0>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x04000510>;

		qcom,initial-pwrlevel = <3>;

		qcom,idle-timeout = <8>; //<HZ/12>
		qcom,strtstp-sleepwake;

		/* Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |
		KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE
		KGSL_CLK_RBBMTIMER */
		qcom,clk-map = <0x000001DE>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
			<&clock_gcc clk_gcc_oxili_ahb_clk>,
			<&clock_gcc clk_gcc_oxili_gmem_clk>,
			<&clock_gcc clk_gcc_bimc_gfx_clk>,
			<&clock_gcc clk_gcc_bimc_gpu_clk>,
			<&clock_gcc clk_gcc_gtcu_ahb_clk>,
			<&clock_gcc clk_gcc_gfx_tcu_clk>,
			<&clock_gcc clk_gcc_oxili_timer_clk>;

		clock-names = "core_clk", "iface_clk", "mem_clk",
				"mem_iface_clk", "alt_mem_iface_clk",
				"gtcu_iface_clk", "gtcu_clk",
				"rbbmtimer_clk";

		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <10>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 512 0 0>,
			<26 512 0 153000>,
			<26 512 0 1600000>,
			<26 512 0 2073000>,
			<26 512 0 3072000>,
			<26 512 0 4147000>,
			<26 512 0 5606000>,
			<26 512 0 5990000>,
			<26 512 0 6451000>,
			<26 512 0 7372000>;

		/* GDSC oxili regulators */
		vdd-supply = <&gdsc_oxili_gx>;

		/* IOMMU Data */
		iommu = <&gfx_iommu>;

		/* Trace bus */
		coresight-id = <67>;
		coresight-name = "coresight-gfx";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <4>;

		/* CPU latency parameter */
		qcom,pm-qos-active-latency = <601>;
		qcom,pm-qos-wakeup-latency = <401>;

		/* Power levels */
		qcom,gpu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			/* TURBO */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <550000000>;
				qcom,bus-freq = <9>;
				qcom,bus-min = <8>;
				qcom,bus-max = <9>;
			};

			/* NOM+ */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <500000000>;
				qcom,bus-freq = <8>;
				qcom,bus-min = <8>;
				qcom,bus-max = <9>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <8>;
			};

			/* SVS+ */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <400000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <6>;
				qcom,bus-max = <7>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <240000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <4>;
				qcom,bus-max = <7>;
			};

			/* XO */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <19200000>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu {
		compatible = "qcom,kgsl-smmu-v2";
		reg = <0x1f00000 0x10000>;
		/*
		* The gpu can only program a single context bank
		* at this fixed offset.
		*/
		qcom,protect = <0x48000 0x1000>;
		clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,
			<&clock_gcc clk_gcc_gfx_tcu_clk>,
			<&clock_gcc clk_gcc_gtcu_ahb_clk>,
			<&clock_gcc clk_gcc_gfx_tbu_clk>;
		clock-names = "iface_clk", "core_clk", "gtcu_iface_clk",
				"gtbu_clk";
		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			qcom,gpu-offset = <0x48000>;
		};
	};
};