/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	mdss_dsi0_pll: qcom,mdss_dsi_pll@994400 {
		compatible = "qcom,mdss_dsi_pll_8996_v2";
		label = "MDSS DSI 0 PLL";
		cell-index = <0>;
		#clock-cells = <1>;

		reg = <0x00994400 0x588>,
		      <0x008C2300 0x8>,
		      <0x00994200 0x98>;
		reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";

		gdsc-supply = <&gdsc_mdss>;

		clocks = <&clock_mmss clk_mdss_ahb_clk>;
		clock-names = "iface_clk";
		clock-rate = <0>;

		/* Memory region for passing dynamic refresh pll codes */
		memory-region = <&dfps_data_mem>;

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "gdsc";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};

		};
	};

	mdss_dsi1_pll: qcom,mdss_dsi_pll@996400 {
		compatible = "qcom,mdss_dsi_pll_8996_v2";
		label = "MDSS DSI 1 PLL";
		cell-index = <1>;
		#clock-cells = <1>;

		reg = <0x00996400 0x588>,
		      <0x008C2300 0x8>,
		      <0x00996200 0x98>;
		reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";

		gdsc-supply = <&gdsc_mdss>;

		clocks = <&clock_mmss clk_mdss_ahb_clk>;
		clock-names = "iface_clk";
		clock-rate = <0>;

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "gdsc";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_hdmi_pll: qcom,mdss_hdmi_pll@0x9a0600 {
		compatible = "qcom,mdss_hdmi_pll_8996";
		label = "MDSS HDMI PLL";
		#clock-cells = <1>;

		reg = <0x9a0600 0xb10>,
		      <0x9a1200 0x0c8>,
		      <0x8C2300 0x8>;
		reg-names = "pll_base", "phy_base", "gdsc_base";

		gdsc-supply = <&gdsc_mdss>;
		vddio-supply = <&pm8994_l12>;
		vcca-supply = <&pm8994_l28>;

		clocks = <&clock_mmss clk_mdss_ahb_clk>,
			 <&clock_gcc clk_gcc_hdmi_clkref_clk>,
			 <&clock_gcc clk_ln_bb_clk>;
		clock-names = "iface_clk", "ref_clk", "ref_clk_src";
		clock-rate = <0>;

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "gdsc";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};

			qcom,platform-supply-entry@1 {
				reg = <1>;
				qcom,supply-name = "vddio";
				qcom,supply-min-voltage = <1800000>;
				qcom,supply-max-voltage = <1800000>;
				qcom,supply-enable-load = <100000>;
				qcom,supply-disable-load = <100>;
			};

			qcom,platform-supply-entry@2 {
				reg = <2>;
				qcom,supply-name = "vcca";
				qcom,supply-min-voltage = <925000>;
				qcom,supply-max-voltage = <925000>;
				qcom,supply-enable-load = <10000>;
				qcom,supply-disable-load = <100>;
			};
		};
	};
};