/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/clock/msm-clocks-cobalt.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM COBALT";
	compatible = "qcom,msmcobalt";
	qcom,msm-id = <292 0x0>;
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uartblsp2dm1;
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};

		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x102>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x103>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	soc: soc { };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		removed_regions: removed_regions@85800000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x85800000 0 0x4f00000>;
		};

		peripheral_mem: peripheral_region@91400000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x91400000 0 0x2d00000>;
		};

		modem_mem: modem_region@8a700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8a700000 0 0x6d00000>;
		};
	};
};

#include "msmcobalt-smp2p.dtsi"
#include "msm-gdsc-cobalt.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,       /* GICD */
		      <0x17b00000 0x100000>;      /* GICR * 8 */
		interrupts = <1 9 4>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	uartblsp1dm1: serial@0c170000 {
		compatible = "qcom,msm-lsuart-v14";
		reg = <0xc170000 0x1000>;
		interrupts = <0 108 0>;
		status = "disabled";
		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
			 <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		clock-names = "core_clk", "iface_clk";
	};

	uartblsp2dm1: serial@0c1b0000 {
		compatible = "qcom,msm-lsuart-v14";
		reg = <0xc1b0000 0x1000>;
		interrupts = <0 114 0>;
		status = "disabled";
		clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
			 <&clock_gcc clk_gcc_blsp2_ahb_clk>;
		clock-names = "core_clk", "iface_clk";
	};

	timer@17920000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17920000 0x1000>;
		clock-frequency = <19200000>;

		frame@17921000 {
			frame-number = <0>;
			interrupts = <0 31 0x4>,
				     <0 30 0x4>;
			reg = <0x17921000 0x1000>,
			      <0x17922000 0x1000>;
		};

		frame@17923000 {
			frame-number = <1>;
			interrupts = <0 32 0x4>;
			reg = <0x17923000 0x1000>;
			status = "disabled";
		};

		frame@17924000 {
			frame-number = <2>;
			interrupts = <0 33 0x4>;
			reg = <0x17924000 0x1000>;
			status = "disabled";
		};

		frame@17925000 {
			frame-number = <3>;
			interrupts = <0 34 0x4>;
			reg = <0x17925000 0x1000>;
			status = "disabled";
		};

		frame@17926000 {
			frame-number = <4>;
			interrupts = <0 35 0x4>;
			reg = <0x17926000 0x1000>;
			status = "disabled";
		};

		frame@17927000 {
			frame-number = <5>;
			interrupts = <0 36 0x4>;
			reg = <0x17927000 0x1000>;
			status = "disabled";
		};

		frame@17928000 {
			frame-number = <6>;
			interrupts = <0 37 0x4>;
			reg = <0x17928000 0x1000>;
			status = "disabled";
		};
	};

	arm64-cpu-erp {
		compatible = "arm,arm64-cpu-erp";
		interrupts = <0 43 4>,
			     <0 44 4>,
			     <0 41 4>,
			     <0 42 4>;

		interrupt-names = "pri-dbe-irq",
				  "sec-dbe-irq",
				  "pri-ext-irq",
				  "sec-ext-irq";

		poll-delay-ms = <5000>;
	};

	clock_gcc: qcom,gcc@100000 {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
	};

	clock_mmss: qcom,mmsscc@c8c0000 {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
	};

	clock_gpu: qcom,gpucc@5065000 {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
	};

	clock_debug: qcom,debugcc@162000 {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
	};

	qcom,ipc-spinlock@1f40000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0x1f40000 0x8000>;
		qcom,num-locks = <8>;
	};

	qcom,smem@86000000 {
		compatible = "qcom,smem";
		reg = <0x86000000 0x200000>,
			<0x17820010 0x4>,
			<0x778000 0x7000>,
			<0x1fd4000 0x8>;
		reg-names = "smem", "irq-reg-base", "aux-mem1",
			"smem_targ_info_reg";
		qcom,mpu-enabled;

		qcom,smd-modem {
			compatible = "qcom,smd";
			qcom,smd-edge = <0>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x1000>;
			interrupts = <0 449 1>;
			label = "modem";
			qcom,not-loadable;
		};

		qcom,smd-adsp {
			compatible = "qcom,smd";
			qcom,smd-edge = <1>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x100>;
			interrupts = <0 156 1>;
			label = "adsp";
		};

		qcom,smd-dsps {
			compatible = "qcom,smd";
			qcom,smd-edge = <3>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x2000000>;
			interrupts = <0 176 1>;
			label = "dsps";
		};
	};

	qcom,smdpkt {
		compatible = "qcom,smdpkt";

		qcom,smdpkt-apr-apps2 {
			qcom,smdpkt-remote = "adsp";
			qcom,smdpkt-port-name = "apr_apps2";
			qcom,smdpkt-dev-name = "apr_apps2";
		};

		qcom,smdpkt-loopback {
			qcom,smdpkt-remote = "modem";
			qcom,smdpkt-port-name = "LOOPBACK";
			qcom,smdpkt-dev-name = "smd_pkt_loopback";
		};
	};

	glink_mpss: qcom,glink-ssr-modem {
		compatible = "qcom,glink_ssr";
		label = "modem";
		qcom,edge = "mpss";
		qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>,
					<&glink_spss>;
		qcom,xprt = "smem";
	};

	glink_lpass: qcom,glink-ssr-adsp {
		compatible = "qcom,glink_ssr";
		label = "adsp";
		qcom,edge = "lpass";
		qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>,
					<&glink_spss>;
		qcom,xprt = "smem";
	};

	glink_dsps: qcom,glink-ssr-dsps {
		compatible = "qcom,glink_ssr";
		label = "slpi";
		qcom,edge = "dsps";
		qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>,
					<&glink_spss>;
		qcom,xprt = "smem";
	};

	glink_rpm: qcom,glink-ssr-rpm {
		compatible = "qcom,glink_ssr";
		label = "rpm";
		qcom,edge = "rpm";
		qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
					<&glink_dsps>, <&glink_spss>;
		qcom,xprt = "smem";
	};

	glink_spss: qcom,glink-ssr-spss {
		compatible = "qcom,glink_ssr";
		label = "spss";
		qcom,edge = "spss";
		qcom,notify-edges = <&glink_mpss>, <&glink_lpass>,
				<&glink_dsps>, <&glink_rpm>;
		qcom,xprt = "mailbox";
	};

	qcom,glink-smem-native-xprt-modem@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x17820010 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x8000>;
		interrupts = <0 452 1>;
		label = "mpss";
	};

	qcom,glink-smem-native-xprt-adsp@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x17820010 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x200>;
		interrupts = <0 157 1>;
		label = "lpass";
	};

	qcom,glink-smem-native-xprt-dsps@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x17820010 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x8000000>;
		interrupts = <0 179 1>;
		label = "dsps";
	};

	qcom,glink-smem-native-xprt-rpm@778000 {
		compatible = "qcom,glink-rpm-native-xprt";
		reg = <0x778000 0x7000>,
			<0x17820010 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x1>;
		interrupts = <0 168 1>;
		label = "rpm";
	};

	qcom,glink-mailbox-xprt-spss@1d05008 {
		compatible = "qcom,glink-mailbox-xprt";
		reg = <0x1d05008 0x8>,
			<0x1d05010 0x4>,
			<0x1d0501c 0x4>,
			<0x1d06008 0x4>;
		reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base",
			"irq-rx-reset";
		qcom,irq-mask = <0x1>;
		interrupts = <0 348 4>;
		label = "spss";
		qcom,tx-ring-size = <0x800>;
		qcom,rx-ring-size = <0x800>;
	};

	qcom,glink_pkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-transport = "smd_trans";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-loopback_cntl {
			qcom,glinkpkt-transport = "lloop";
			qcom,glinkpkt-edge = "local";
			qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
			qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
		};

		qcom,glinkpkt-loopback_data {
			qcom,glinkpkt-transport = "lloop";
			qcom,glinkpkt-edge = "local";
			qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
			qcom,glinkpkt-dev-name = "glink_pkt_loopback";
		};
	};

	qcom,ipc_router {
		compatible = "qcom,ipc_router";
		qcom,node-id = <1>;
	};

	qcom,ipc_router_modem_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "mpss";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_q6_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "lpass";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_dsps_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "dsps";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	sdhc_2: sdhci@c0a4900 {
		compatible = "qcom,sdhci-msm";
		reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
		reg-names = "hc_mem", "core_mem";

		interrupts = <0 125 0>, <0 221 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
			 <&clock_gcc clk_gcc_sdcc2_apps_clk>;

		qcom,large-address-bus;
		qcom,bus-width = <4>;
		qcom,cpu-dma-latency-us = <701>;

		qcom,devfreq,freq-table = <52000000 200000000>;

		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <8>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
				<81 512 1600 3200>,    /* 400 KB/s*/
				<81 512 80000 160000>, /* 20 MB/s */
				<81 512 100000 200000>, /* 25 MB/s */
				<81 512 200000 400000>, /* 50 MB/s */
				<81 512 400000 800000>, /* 100 MB/s */
				<81 512 800000 800000>, /* 200 MB/s */
				<81 512 2048000 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
						100000000 200000000 4294967295>;

		status = "disabled";
	};

	ufsphy1: ufsphy@1da7000 {
		compatible = "qcom,ufs-phy-qmp-v3";
		reg = <0x1da7000 0xda8>;
		reg-names = "phy_mem";
		#phy-cells = <0>;
		vdda-phy-max-microamp = <51430>;
		vdda-pll-max-microamp = <14170>;
		vddp-ref-clk-max-microamp = <100>;
		vddp-ref-clk-always-on;
		clock-names = "ref_clk_src",
			"ref_clk";
		clocks = <&clock_gcc clk_ln_bb_clk1>,
			<&clock_gcc clk_gcc_ufs_clkref_clk>;
		status = "disabled";
	};

	ufs1: ufshc@1da4000 {
		compatible = "jedec,ufs-1.1";
		reg = <0x1da4000 0x2500>;
		interrupts = <0 265 0>;
		phys = <&ufsphy1>;
		phy-names = "ufsphy";
		vdd-hba-supply = <&gdsc_ufs>;
		vdd-hba-fixed-regulator;
		vcc-max-microamp = <750000>;
		vccq-max-microamp = <450000>;
		vccq2-max-microamp = <750000>;

		clock-names =
			"core_clk_src",
			"core_clk",
			"iface_clk",
			"core_clk_unipro_src",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk";
		clocks =
			<&clock_gcc clk_ufs_axi_clk_src>,
			<&clock_gcc clk_gcc_ufs_axi_clk>,
			<&clock_gcc clk_gcc_ufs_ahb_clk>,
			<&clock_gcc clk_ufs_ice_core_clk_src>,
			<&clock_gcc clk_gcc_ufs_unipro_core_clk>,
			<&clock_gcc clk_gcc_ufs_ice_core_clk>,
			<&clock_gcc clk_ln_bb_clk1>,
			<&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
			<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;
		freq-table-hz =
			<100000000 200000000>,
			<0 0>,
			<0 0>,
			<150000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		lanes-per-direction = <1>;
		qcom,msm-bus,name = "ufs1";
		qcom,msm-bus,num-cases = <12>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		<95 512 0 0>, <1 650 0 0>,          /* No vote */
		<95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */
		<95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */
		<95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */
		<95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */
		<95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */
		<95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */
		<95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */
		<95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */
		<95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */
		<95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */
		<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"MAX";

		qcom,cpu-affinity = "affine_cores";
		qcom,cpu-dma-latency-us = <301>;

		status = "disabled";

		ufs_variant {
			compatible = "qcom,ufs_variant";
		};
	};

	usb3: ssusb@a800000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x0a800000 0xf8c00>,
		      <0x0c016000 0x400>;
		reg-names = "core_base", "ahb2phy_base";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <0 133 0>, <0 180 0>;
		interrupt-names = "hs_phy_irq", "pwr_event_irq";

		USB3_GDSC-supply = <&gdsc_usb30>;
		qcom,msm-bus,name = "usb3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
					<61 512 0 0>,
					<61 512 240000 960000>;

		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
		qcom,power-collapse-on-cable-disconnect;
		qcom,por-after-power-collapse;

		clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
			<&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
			<&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,
			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
			<&clock_gcc clk_gcc_usb30_sleep_clk>,
			<&clock_gcc clk_cxo_dwc3_clk>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
				"utmi_clk", "sleep_clk", "xo";

		dwc3@a800000 {
			compatible = "snps,dwc3";
			reg = <0x0a800000 0xcd00>;
			interrupt-parent = <&intc>;
			interrupts = <0 131 0>;
			usb-phy = <&qusb_phy0>, <&ssphy>;
			tx-fifo-resize;
			snps,usb3-u1u2-disable;
			snps,nominal-elastic-buffer;
			snps,hird_thresh = <0x10>;
		};
	 };

	android_usb {
		compatible = "qcom,android-usb";
	};

	qusb_phy0: qusb@c012200 {
		compatible = "qcom,qusb2phy";
		reg = <0x0c012200 0xb0>,
		      <0x0a8f8800 0x400>,
			<0x0078024c 0x4>;
		reg-names = "qusb_phy_base",
			"qscratch_base",
			"tune2_efuse_addr";
		vdd-supply = <&pmcobalt_l1>;
		vdda18-supply = <&pmcobalt_l12>;
		vdda33-supply = <&pmcobalt_l24>;
		qcom,vdd-voltage-level = <0 880000 880000>;
		phy_type= "utmi";

		clocks = <&clock_gcc clk_ln_bb_clk1>,
			 <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>,
			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
			 <&clock_gcc clk_gcc_qusb2phy_prim_reset>;

		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",
			      "phy_reset";
	};

	ssphy: ssphy@c010000 {
		compatible = "qcom,usb-ssphy-qmp-v2";
		reg = <0x0c010000 0xbf8>,
		      <0x01fcb244 0x4>;
		reg-names = "qmp_phy_base",
			    "vls_clamp_reg";
		vdd-supply = <&pmcobalt_l1>;
		vdda18-supply = <&pmcobalt_l12>;
		qcom,vdd-voltage-level = <0 880000 880000>;
		qcom,vbus-valid-override;

		clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
			 <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
			 <&clock_gcc clk_gcc_usb3_phy_reset>,
			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,
			 <&clock_gcc clk_ln_bb_clk1>,
			 <&clock_gcc clk_gcc_usb3_clkref_clk>;

		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
			      "phy_phy_reset", "ref_clk_src", "ref_clk";
	};

	qcom,lpass@17300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x17300000 0x00100>;
		interrupts = <0 162 1>;

		vdd_cx-supply = <&pmcobalt_s1_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_gcc clk_cxo_pil_lpass_clk>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&peripheral_mem>;

		/* GPIO inputs from lpass */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;

		/* GPIO output to lpass */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
	};
};

#include "msmcobalt-regulator.dtsi"

&gdsc_mmss {
	status = "ok";
};

&gdsc_usb30 {
	clock-names = "core_clk";
	clocks = <&clock_gcc clk_gcc_usb30_master_clk>;
	status = "ok";
};

&gdsc_pcie_0 {
	clock-names = "master_bus_clk", "slave_bus_clk", "core_clk";
	clocks = <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
		 <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
		 <&clock_gcc clk_gcc_pcie_0_pipe_clk>;
	status = "ok";
};

&gdsc_ufs {
	clock-names = "bus_clk", "ice_clk", "unipro_clk";
	clocks = <&clock_gcc clk_gcc_ufs_axi_clk>,
		 <&clock_gcc clk_gcc_ufs_ice_core_clk>,
		 <&clock_gcc clk_gcc_ufs_unipro_core_clk>;
	status = "ok";
};

&gdsc_bimc_smmu {
	clock-names = "bus_clk";
	clocks = <&clock_gcc clk_bimc_smmu_axi_clk>;
	status = "ok";
};

&gdsc_hlos1_vote_gpu_smmu {
	status = "ok";
};

&gdsc_hlos1_vote_lpass_adsp {
	status = "ok";
};

&gdsc_hlos1_vote_lpass_core {
	status = "ok";
};

&gdsc_venus {
	clock-names = "bus_clk", "maxi_clk", "core_clk";
	clocks = <&clock_mmss clk_video_axi_clk>,
		 <&clock_mmss clk_video_maxi_clk>,
		 <&clock_mmss clk_video_core_clk>;
	status = "ok";
};

&gdsc_venus_core0 {
	clock-names = "core0_clk";
	clocks = <&clock_mmss clk_video_subcore0_clk>;
	status = "ok";
};

&gdsc_venus_core1 {
	clock-names = "core1_clk";
	clocks = <&clock_mmss clk_video_subcore1_clk>;
	status = "ok";
};

&gdsc_camss_top {
	clock-names = "bus_clk", "vfe_axi";
	clocks = <&clock_mmss clk_camss_cpp_axi_clk>,
		 <&clock_mmss clk_camss_vfe_vbif_axi_clk>;
	status = "ok";
};

&gdsc_vfe0 {
	clock-names = "core0_clk" , "core0_stream_clk";
	clocks = <&clock_mmss clk_camss_vfe0_clk>,
		 <&clock_mmss clk_camss_vfe0_stream_clk>;
	parent-supply = <&gdsc_camss_top>;
	status = "ok";
};

&gdsc_vfe1 {
	clock-names = "core1_clk" , "core1_stream_clk";
	clocks = <&clock_mmss clk_camss_vfe1_clk>,
		 <&clock_mmss clk_camss_vfe1_stream_clk>;
	parent-supply = <&gdsc_camss_top>;
	status = "ok";
};

&gdsc_cpp {
	clock-names = "core_clk";
	clocks = <&clock_mmss clk_camss_cpp_clk>;
	parent-supply = <&gdsc_camss_top>;
	status = "ok";
};

&gdsc_mdss {
	clock-names = "bus_clk", "core_clk", "root_clk";
	clocks = <&clock_mmss clk_mdss_axi_clk>,
		 <&clock_mmss clk_mdss_mdp_clk>,
		 <&clock_mmss clk_mdss_rot_clk>;
	status = "ok";
};

&gdsc_gpu_gx {
	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
	clocks = <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>,
		 <&clock_gpu clk_gfx3d_clk>,
		 <&clock_gpu clk_gfx3d_clk_src>;
	qcom,force-enable-root-clk;
	parent-supply = <&pm8005_s1>;
	status = "ok";
};

&gdsc_gpu_cx {
	status = "ok";
};