/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/clock/msm-clocks-titanium.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM Titanium";
	compatible = "qcom,msmtitanium";
	qcom,msm-id = <293 0x0>;
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		other_ext_mem: other_ext_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x85e00000 0x0 0xa00000>;
		};

		modem_mem: modem_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86800000 0x0 0x6a00000>;
		};

		reloc_mem: reloc_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x8d200000 0x0 0x1b00000>;
		};

		venus_mem: venus_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
			alignment = <0 0x400000>;
			size = <0 0x0800000>;
		};

		secure_mem: secure_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x7000000>;
		};

		qseecom_mem: qseecom_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		adsp_mem: adsp_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x400000>;
		};
	};

	aliases {
		/* smdtty devices */
		smd1 = &smdtty_apps_fm;
		smd2 = &smdtty_apps_riva_bt_acl;
		smd3 = &smdtty_apps_riva_bt_cmd;
		smd4 = &smdtty_mbalbridge;
		smd5 = &smdtty_apps_riva_ant_cmd;
		smd6 = &smdtty_apps_riva_ant_data;
		smd7 = &smdtty_data1;
		smd8 = &smdtty_data4;
		smd11 = &smdtty_data11;
		smd21 = &smdtty_data21;
		smd36 = &smdtty_loopback;
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
	};

	soc: soc { };

};

#include "msmtitanium-pinctrl.dtsi"
#include "msmtitanium-cpu.dtsi"
#include "msmtitanium-ion.dtsi"
#include "msmtitanium-smp2p.dtsi"
#include "msm-arm-smmu-titanium.dtsi"
#include "msmtitanium-coresight.dtsi"
#include "msmtitanium-iommu-domains.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@b000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x0b000000 0x1000>,
		      <0x0b002000 0x1000>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 2 0xff08>,
			     <1 3 0xff08>,
			     <1 4 0xff08>,
			     <1 1 0xff08>;
		clock-frequency = <19200000>;
	};

	timer@b120000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0xb120000 0x1000>;
		clock-frequency = <19200000>;

		frame@b121000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 7 0x4>;
			reg = <0xb121000 0x1000>,
			      <0xb122000 0x1000>;
		};

		frame@b123000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0xb123000 0x1000>;
			status = "disabled";
		};

		frame@b124000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0xb124000 0x1000>;
			status = "disabled";
		};

		frame@b125000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0xb125000 0x1000>;
			status = "disabled";
		};

		frame@b126000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0xb126000 0x1000>;
			status = "disabled";
		};

		frame@b127000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0xb127000 0x1000>;
			status = "disabled";
		};

		frame@b128000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0xb128000 0x1000>;
			status = "disabled";
		};
	};

	restart@4ab000 {
		compatible = "qcom,pshold";
		reg = <0x4ab000 0x4>,
			<0x193d100 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom,mpm2-sleep-counter@4a3000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0x4a3000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,sps {
		compatible = "qcom,msm_sps_4k";
		qcom,pipe-attr-ee;
	};

	tsens: tsens@4a8000 {
		compatible = "qcom,msmtitanium-tsens";
		reg = <0x4a8000 0x2000>,
			<0xa4000 0x1000>;
		reg-names = "tsens_physical", "tsens_eeprom_physical";
		interrupts = <0 184 0>, <0 314 0>;
		interrupt-names = "tsens-upper-lower", "tsens-critical";
		qcom,sensors = <16>;
		qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
					3200 3200 3200 3200 3200 3200 3200>;
	};

	blsp1_uart2: serial@78b0000 {
		compatible = "qcom,msm-lsuart-v14";
		reg = <0x78b0000 0x200>;
		interrupts = <0 108 0>;
		status = "disabled";
		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
		<&clock_gcc clk_gcc_blsp1_ahb_clk>;
		clock-names = "core_clk", "iface_clk";
	};

	clock_gcc: qcom,gcc {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
	};

	dcc: dcc@b3000 {
		compatible = "qcom,dcc";
		reg = <0xb3000 0x1000>,
		      <0xb4000 0x2000>;
		reg-names = "dcc-base", "dcc-ram-base";

		clocks = <&clock_gcc clk_gcc_dcc_clk>;
		clock-names = "dcc_clk";

		qcom,save-reg;
	};

	qcom,ipc-spinlock@1905000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0x1905000 0x8000>;
		qcom,num-locks = <8>;
	};

	qcom,smem@86300000 {
		compatible = "qcom,smem";
		reg = <0x86300000 0x100000>,
			<0x0b011008 0x4>,
			<0x60000 0x8000>,
			<0x193d000 0x8>;
		reg-names = "smem", "irq-reg-base",
				"aux-mem1", "smem_targ_info_reg";
		qcom,mpu-enabled;

		qcom,smd-modem {
			compatible = "qcom,smd";
			qcom,smd-edge = <0>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x1000>;
			interrupts = <0 25 1>;
			label = "modem";
		};

		qcom,smsm-modem {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <0>;
			qcom,smsm-irq-offset = <0x0>;
			qcom,smsm-irq-bitmask = <0x2000>;
			interrupts = <0 26 1>;
		};

		qcom,smd-wcnss {
			compatible = "qcom,smd";
			qcom,smd-edge = <6>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x20000>;
			interrupts = <0 142 1>;
			label = "wcnss";
		};

		qcom,smsm-wcnss {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <6>;
			qcom,smsm-irq-offset = <0x0>;
			qcom,smsm-irq-bitmask = <0x80000>;
			interrupts = <0 144 1>;
		};

		qcom,smd-adsp {
			compatible = "qcom,smd";
			qcom,smd-edge = <1>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x100>;
			interrupts = <0 289 1>;
			label = "adsp";
		};

		qcom,smsm-adsp {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <1>;
			qcom,smsm-irq-offset = <0x0>;
			qcom,smsm-irq-bitmask = <0x200>;
			interrupts = <0 290 1>;
		};

		qcom,smd-rpm {
			compatible = "qcom,smd";
			qcom,smd-edge = <15>;
			qcom,smd-irq-offset = <0x0>;
			qcom,smd-irq-bitmask = <0x1>;
			interrupts = <0 168 1>;
			label = "rpm";
			qcom,irq-no-suspend;
			qcom,not-loadable;
		};
	};

	qcom,wdt@b017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xb017000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <0 3 0>, <0 4 0>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <10000>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
		status = "disabled";
	};

	qcom,msm-imem@8600000 {
		compatible = "qcom,msm-imem";
		reg = <0x08600000 0x1000>;
		ranges = <0x0 0x08600000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 32>;
		};
	};

	qcom,smdtty {
		compatible = "qcom,smdtty";

		smdtty_apps_fm: qcom,smdtty-apps-fm {
			qcom,smdtty-remote = "wcnss";
			qcom,smdtty-port-name = "APPS_FM";
		};

		smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl {
			qcom,smdtty-remote = "wcnss";
			qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
		};

		smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd {
			qcom,smdtty-remote = "wcnss";
			qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
		};

		smdtty_mbalbridge: qcom,smdtty-mbalbridge {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "MBALBRIDGE";
		};

		smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd {
			qcom,smdtty-remote = "wcnss";
			qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
		};

		smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data {
			qcom,smdtty-remote = "wcnss";
			qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
		};

		smdtty_data1: qcom,smdtty-data1 {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "DATA1";
		};

		smdtty_data4: qcom,smdtty-data4 {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "DATA4";
		};

		smdtty_data11: qcom,smdtty-data11 {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "DATA11";
		};

		smdtty_data21: qcom,smdtty-data21 {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "DATA21";
		};

		smdtty_loopback: smdtty-loopback {
			qcom,smdtty-remote = "modem";
			qcom,smdtty-port-name = "LOOPBACK";
			qcom,smdtty-dev-name = "LOOPBACK_TTY";
		};
	};

	qcom,smdpkt {
		compatible = "qcom,smdpkt";

		qcom,smdpkt-data5-cntl {
			qcom,smdpkt-remote = "modem";
			qcom,smdpkt-port-name = "DATA5_CNTL";
			qcom,smdpkt-dev-name = "smdcntl0";
		};

		qcom,smdpkt-data22 {
			qcom,smdpkt-remote = "modem";
			qcom,smdpkt-port-name = "DATA22";
			qcom,smdpkt-dev-name = "smd22";
		};

		qcom,smdpkt-data40-cntl {
			qcom,smdpkt-remote = "modem";
			qcom,smdpkt-port-name = "DATA40_CNTL";
			qcom,smdpkt-dev-name = "smdcntl8";
		};

		qcom,smdpkt-apr-apps2 {
			qcom,smdpkt-remote = "adsp";
			qcom,smdpkt-port-name = "apr_apps2";
			qcom,smdpkt-dev-name = "apr_apps2";
		};

		qcom,smdpkt-loopback {
			qcom,smdpkt-remote = "modem";
			qcom,smdpkt-port-name = "LOOPBACK";
			qcom,smdpkt-dev-name = "smd_pkt_loopback";
		};
	};

	qcom,ipc_router {
		compatible = "qcom,ipc_router";
		qcom,node-id = <1>;
		qcom,default-peripheral = "modem";
	};

	qcom,ipc_router_modem_xprt {
		compatible = "qcom,ipc_router_smd_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "modem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_q6_xprt {
		compatible = "qcom,ipc_router_smd_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "adsp";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_wcnss_xprt {
		compatible = "qcom,ipc_router_smd_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "wcnss";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
	};

	qcom,adsprpc_domains {
		compatible = "qcom,msm-fastrpc-legacy-compute-cb";
		qcom,msm_fastrpc_compute_cb {
			qcom,adsp-shared-domain-phandle = <&adsp_shared_domain>;
			qcom,adsp-shared-sids =
					<0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
		};
	};

	sdhc_1: sdhci@7824900 {
		compatible = "qcom,sdhci-msm";
		reg = <0x7824900 0x500>, <0x7824000 0x800>;
		reg-names = "hc_mem", "core_mem";

		interrupts = <0 123 0>, <0 138 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <8>;

		qcom,devfreq,freq-table = <52000000 200000000>;

		qcom,cpu-dma-latency-us = <60 340 900>;

		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <9>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
			<78 512 1046 3200>,    /* 400 KB/s*/
			<78 512 52286 160000>, /* 20 MB/s */
			<78 512 65360 200000>, /* 25 MB/s */
			<78 512 130718 400000>, /* 50 MB/s */
			<78 512 130718 400000>, /* 100 MB/s */
			<78 512 261438 800000>, /* 200 MB/s */
			<78 512 261438 800000>, /* 400 MB/s */
			<78 512 1338562 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
			100000000 200000000 400000000 4294967295>;

		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;
		clock-names = "iface_clk", "core_clk";
	};

	spmi_bus: qcom,spmi@200f000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x200f000 0x1000>,
			<0x2400000 0x800000>,
			<0x2c00000 0x800000>,
			<0x3800000 0x200000>,
			<0x200a000 0x2100>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupts = <0 190 0>;
		qcom,pmic-arb-channel = <0>;
		qcom,pmic-arb-max-peripherals = <256>;
		qcom,pmic-arb-max-periph-interrupts = <256>;
		qcom,pmic-arb-ee = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		#address-cells = <1>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,not-wakeup; /* Needed until MPM is fully configured. */
		status = "disabled";
	};

	qcom,lpass@c200000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xc200000 0x00100>;
		interrupts = <0 293 1>;

		vdd_cx-supply = <&pmtitanium_s2_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_gcc clk_xo_pil_lpass_clk>,
			 <&clock_gcc clk_gcc_crypto_clk>,
			 <&clock_gcc clk_gcc_crypto_ahb_clk>,
			 <&clock_gcc clk_gcc_crypto_axi_clk>,
			 <&clock_gcc clk_crypto_clk_src>;
		clock-names = "xo", "scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";
		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
				 "scm_bus_clk", "scm_core_clk_src";
		qcom,scm_core_clk_src-freq = <80000000>;

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";

		/* GPIO inputs from lpass */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;

		/* GPIO output to lpass */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;

		memory-region = <&reloc_mem>;
	};

	qcom,venus@1de0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x1de0000 0x4000>;

		vdd-supply = <&gdsc_venus>;
		qcom,proxy-reg-names = "vdd";

		clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,
			 <&clock_gcc clk_gcc_venus0_ahb_clk>,
			 <&clock_gcc clk_gcc_venus0_axi_clk>,
			 <&clock_gcc clk_gcc_crypto_clk>,
			 <&clock_gcc clk_gcc_crypto_ahb_clk>,
			 <&clock_gcc clk_gcc_crypto_axi_clk>,
			 <&clock_gcc clk_crypto_clk_src>;

		clock-names = "core_clk", "iface_clk", "bus_clk",
				"scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "core_clk", "iface_clk",
					 "bus_clk", "scm_core_clk",
					 "scm_iface_clk", "scm_bus_clk",
					 "scm_core_clk_src";
		qcom,scm_core_clk_src-freq = <80000000>;

		qcom,msm-bus,name = "pil-venus";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<63 512 0 0>,
				<63 512 0 304000>;

		qcom,pas-id = <9>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&venus_mem>;
	};

	qcom,pronto@a21b000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x0a21b000 0x3000>;
		interrupts = <0 149 1>;

		vdd_pronto_pll-supply = <&pmtitanium_l7>;
		proxy-reg-names = "vdd_pronto_pll";
		vdd_pronto_pll-uV-uA = <1800000 18000>;
		clocks = <&clock_gcc clk_xo_pil_pronto_clk>,
			 <&clock_gcc clk_gcc_crypto_clk>,
			 <&clock_gcc clk_gcc_crypto_ahb_clk>,
			 <&clock_gcc clk_gcc_crypto_axi_clk>,
			 <&clock_gcc clk_crypto_clk_src>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";
		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
				 "scm_bus_clk", "scm_core_clk_src";
		qcom,scm_core_clk_src = <80000000>;

		qcom,pas-id = <6>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <422>;
		qcom,sysmon-id = <6>;
		qcom,ssctl-instance-id = <0x13>;
		qcom,firmware-name = "wcnss";

		/* GPIO inputs from wcnss */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>;

		/* GPIO output to wcnss */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
		memory-region = <&reloc_mem>;
	};

	usb3: ssusb@7000000{
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x07000000 0xfc000>,
		      <0x7E000 0x400>;
		reg-names = "core_base",
			"ahb2phy_base";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <0 136 0>, <0 134 0>;
		interrupt-names = "hs_phy_irq", "pwr_event_irq";

		USB3_GDSC-supply = <&gdsc_usb30>;
		vbus_dwc3-supply = <&smbcharger_charger_otg>;
		qcom,usb-dbm = <&dbm_1p5>;
		qcom,msm-bus,name = "usb3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
					<87 512 0 0>,
					<87 512 240000 960000>;

		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;

		clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
			<&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>,
			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
			<&clock_gcc clk_gcc_usb30_sleep_clk>,
			<&clock_gcc clk_xo_dwc3_clk>;

		clock-names = "core_clk", "iface_clk", "utmi_clk",
				"sleep_clk", "xo";

		dwc3@7000000 {
			compatible = "snps,dwc3";
			reg = <0x07000000 0xc8d0>;
			interrupt-parent = <&intc>;
			interrupts = <0 140 0>;
			usb-phy = <&qusb_phy>, <&ssphy>;
			tx-fifo-resize;
			snps,usb3-u1u2-disable;
			snps,nominal-elastic-buffer;
			snps,is-utmi-l1-suspend;
			snps,hird-threshold = /bits/ 8 <0x0>;
		};

		qcom,usbbam@7104000 {
			compatible = "qcom,usb-bam-msm";
			reg = <0x07104000 0x1a934>;
			interrupt-parent = <&intc>;
			interrupts = <0 135 0>;

			qcom,bam-type = <0>;
			qcom,usb-bam-fifo-baseaddr = <0x08605000>;
			qcom,usb-bam-num-pipes = <8>;
			qcom,ignore-core-reset-ack;
			qcom,disable-clk-gating;
			qcom,usb-bam-override-threshold = <0x4001>;
			qcom,usb-bam-max-mbps-highspeed = <400>;
			qcom,usb-bam-max-mbps-superspeed = <3600>;
			qcom,reset-bam-on-connect;

			qcom,pipe0 {
				label = "ssusb-ipa-out-0";
				qcom,usb-bam-mem-type = <1>;
				qcom,dir = <0>;
				qcom,pipe-num = <0>;
				qcom,peer-bam = <1>;
				qcom,src-bam-pipe-index = <1>;
				qcom,data-fifo-size = <0x8000>;
				qcom,descriptor-fifo-size = <0x2000>;
			};

			qcom,pipe1 {
				label = "ssusb-ipa-in-0";
				qcom,usb-bam-mem-type = <1>;
				qcom,dir = <1>;
				qcom,pipe-num = <0>;
				qcom,peer-bam = <1>;
				qcom,dst-bam-pipe-index = <0>;
				qcom,data-fifo-size = <0x8000>;
				qcom,descriptor-fifo-size = <0x2000>;
			};

			qcom,pipe2 {
				label = "ssusb-qdss-in-0";
				qcom,usb-bam-mem-type = <2>;
				qcom,dir = <1>;
				qcom,pipe-num = <0>;
				qcom,peer-bam = <0>;
				qcom,peer-bam-physical-address = <0x06044000>;
				qcom,src-bam-pipe-index = <0>;
				qcom,dst-bam-pipe-index = <2>;
				qcom,data-fifo-offset = <0x0>;
				qcom,data-fifo-size = <0xe00>;
				qcom,descriptor-fifo-offset = <0xe00>;
				qcom,descriptor-fifo-size = <0x200>;
			};

			qcom,pipe3 {
				label = "ssusb-dpl-ipa-in-1";
				qcom,usb-bam-mem-type = <1>;
				qcom,dir = <1>;
				qcom,pipe-num = <1>;
				qcom,peer-bam = <1>;
				qcom,dst-bam-pipe-index = <2>;
				qcom,data-fifo-size = <0x8000>;
				qcom,descriptor-fifo-size = <0x2000>;
			};
		};
	};

	qusb_phy: qusb@79000 {
		compatible = "qcom,qusb2phy";
		reg = <0x079000 0x180>,
			<0x070f8800 0x400>;
		reg-names = "qusb_phy_base",
			"qscratch_base";

		vdd-supply = <&pmtitanium_s7_level>;
		vdda18-supply = <&pmtitanium_l7>;
		vdda33-supply = <&pmtitanium_l13>;
		qcom,vdd-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NONE
					RPM_SMD_REGULATOR_LEVEL_NOM
					RPM_SMD_REGULATOR_LEVEL_TURBO>;

		qcom,qusb-phy-init-seq = <0xF8 0x80
					0xB3 0x84
					0x83 0x88
					0xC0 0x8C
					0x30 0x08
					0x79 0x0C
					0x21 0x10
					0x14 0x9C
					0x80 0x04
					0x9F 0x1C
					0x00 0x18>;
		phy_type= "utmi";

		clocks = <&clock_gcc clk_bb_clk1>,
			 <&clock_gcc clk_gcc_qusb_ref_clk>,
			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,
			 <&clock_gcc clk_gcc_qusb2_phy_reset>;

		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",
			      "phy_reset";

	};

	ssphy: ssphy@78000 {
		compatible = "qcom,usb-ssphy-qmp-v2";
		reg = <0x78000 0x45C>,
		      <0x0193F244 0x4>;
		reg-names = "qmp_phy_base",
			    "vls_clamp_reg";
		vdd-supply = <&pmtitanium_l3>;
		vdda18-supply = <&pmtitanium_l7>;
		qcom,vdd-voltage-level = <0 925000 925000>;
		qcom,vbus-valid-override;

		clocks = <&clock_gcc clk_gcc_usb3_aux_clk>,
			 <&clock_gcc clk_gcc_usb3_pipe_clk>,
			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,
			 <&clock_gcc clk_gcc_usb3_phy_reset>,
			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,
			 <&clock_gcc clk_bb_clk1>,
			 <&clock_gcc clk_gcc_usb_ss_ref_clk>;

		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
			      "phy_phy_reset", "ref_clk_src", "ref_clk";

	};

	dbm_1p5: dbm@70f8000 {
		compatible = "qcom,usb-dbm-1p5";
		reg = <0x070f8000 0x300>;
		qcom,reset-ep-after-lpm-resume;
	};

	android_usb@86000c8 {
		compatible = "qcom,android-usb";
		reg = <0x086000c8 0xc8>;
	};
};

#include "msmtitanium-regulator.dtsi"
#include "msm-pmtitanium.dtsi"
#include "msm-pmi8950.dtsi"
#include "msm-gdsc-8916.dtsi"

&gdsc_venus {
	status = "okay";
};

&gdsc_venus_core0 {
	status = "okay";
};

&gdsc_mdss {
	status = "okay";
};

&gdsc_oxili_gx {
	status = "okay";
};

&gdsc_jpeg {
	status = "okay";
};

&gdsc_vfe {
	status = "okay";
};

&gdsc_vfe1 {
	status = "okay";
};

&gdsc_cpp {
	status = "okay";
};

&gdsc_oxili_cx {
	status = "okay";
};

&gdsc_usb30 {
	status = "okay";
};

&pmtitanium_mpps {
	mpp@a100 {
		/* MPP2 - PA_THERM config */
		qcom,mode = <4>; /* AIN input */
		qcom,invert = <1>; /* Enable MPP */
		qcom,ain-route = <1>; /* AMUX 6 */
		qcom,master-en = <1>;
		qcom,src-sel = <0>; /* Function constant */
	};

	mpp@a300 {
		/* MPP4 - CASE_THERM config */
		qcom,mode = <4>; /* AIN input */
		qcom,invert = <1>; /* Enable MPP */
		qcom,ain-route = <3>; /* AMUX 8 */
		qcom,master-en = <1>;
		qcom,src-sel = <0>; /* Function constant */
	};
};

&pmtitanium_vadc {
	chan@5 {
		label = "vcoin";
		reg = <5>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <1>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <0>;
		qcom,hw-settle-time = <0>;
		qcom,fast-avg-setup = <0>;
	};

	chan@7 {
		label = "vph_pwr";
		reg = <7>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <1>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <0>;
		qcom,hw-settle-time = <0>;
		qcom,fast-avg-setup = <0>;
	};

	chan@36 {
		label = "pa_therm0";
		reg = <0x36>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <2>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
	};

	chan@11 {
		label = "pa_therm1";
		reg = <0x11>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <2>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
		qcom,vadc-thermal-node;
	};

	chan@32 {
		label = "xo_therm";
		reg = <0x32>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <4>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
		qcom,vadc-thermal-node;
	};

	chan@3c {
		label = "xo_therm_buf";
		reg = <0x3c>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <4>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
		qcom,vadc-thermal-node;
	};

	chan@13 {
		label = "case_therm";
		reg = <0x13>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "ratiometric";
		qcom,scale-function = <2>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
		qcom,vadc-thermal-node;
	};
};

&pmtitanium_adc_tm {
	chan@36 {
		label = "pa_therm0";
		reg = <0x36>;
		qcom,decimation = <0>;
		qcom,pre-div-channel-scaling = <0>;
		qcom,calibration-type = "absolute";
		qcom,scale-function = <2>;
		qcom,hw-settle-time = <2>;
		qcom,fast-avg-setup = <0>;
		qcom,btm-channel-number = <0x48>;
		qcom,thermal-node;
	};
};