234 lines
5.5 KiB
C
234 lines
5.5 KiB
C
/*
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* Emulation of the "brl" instruction for IA64 processors that
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* don't support it in hardware.
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* Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com>
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*
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* 02/22/02 D. Mosberger Clear si_flgs, si_isr, and si_imm to avoid
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* leaking kernel bits.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <asm/uaccess.h>
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#include <asm/processor.h>
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extern char ia64_set_b1, ia64_set_b2, ia64_set_b3, ia64_set_b4, ia64_set_b5;
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struct illegal_op_return {
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unsigned long fkt, arg1, arg2, arg3;
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};
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/*
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* The unimplemented bits of a virtual address must be set
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* to the value of the most significant implemented bit.
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* unimpl_va_mask includes all unimplemented bits and
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* the most significant implemented bit, so the result
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* of an and operation with the mask must be all 0's
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* or all 1's for the address to be valid.
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*/
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#define unimplemented_virtual_address(va) ( \
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((va) & local_cpu_data->unimpl_va_mask) != 0 && \
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((va) & local_cpu_data->unimpl_va_mask) != local_cpu_data->unimpl_va_mask \
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)
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/*
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* The unimplemented bits of a physical address must be 0.
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* unimpl_pa_mask includes all unimplemented bits, so the result
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* of an and operation with the mask must be all 0's for the
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* address to be valid.
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*/
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#define unimplemented_physical_address(pa) ( \
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((pa) & local_cpu_data->unimpl_pa_mask) != 0 \
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)
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/*
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* Handle an illegal operation fault that was caused by an
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* unimplemented "brl" instruction.
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* If we are not successful (e.g because the illegal operation
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* wasn't caused by a "brl" after all), we return -1.
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* If we are successful, we return either 0 or the address
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* of a "fixup" function for manipulating preserved register
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* state.
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*/
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struct illegal_op_return
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ia64_emulate_brl (struct pt_regs *regs, unsigned long ar_ec)
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{
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unsigned long bundle[2];
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unsigned long opcode, btype, qp, offset, cpl;
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unsigned long next_ip;
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struct siginfo siginfo;
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struct illegal_op_return rv;
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long tmp_taken, unimplemented_address;
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rv.fkt = (unsigned long) -1;
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/*
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* Decode the instruction bundle.
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*/
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if (copy_from_user(bundle, (void *) (regs->cr_iip), sizeof(bundle)))
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return rv;
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next_ip = (unsigned long) regs->cr_iip + 16;
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/* "brl" must be in slot 2. */
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if (ia64_psr(regs)->ri != 1) return rv;
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/* Must be "mlx" template */
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if ((bundle[0] & 0x1e) != 0x4) return rv;
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opcode = (bundle[1] >> 60);
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btype = ((bundle[1] >> 29) & 0x7);
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qp = ((bundle[1] >> 23) & 0x3f);
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offset = ((bundle[1] & 0x0800000000000000L) << 4)
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| ((bundle[1] & 0x00fffff000000000L) >> 32)
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| ((bundle[1] & 0x00000000007fffffL) << 40)
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| ((bundle[0] & 0xffff000000000000L) >> 24);
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tmp_taken = regs->pr & (1L << qp);
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switch(opcode) {
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case 0xC:
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/*
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* Long Branch.
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*/
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if (btype != 0) return rv;
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rv.fkt = 0;
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if (!(tmp_taken)) {
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/*
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* Qualifying predicate is 0.
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* Skip instruction.
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*/
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regs->cr_iip = next_ip;
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ia64_psr(regs)->ri = 0;
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return rv;
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}
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break;
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case 0xD:
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/*
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* Long Call.
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*/
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rv.fkt = 0;
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if (!(tmp_taken)) {
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/*
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* Qualifying predicate is 0.
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* Skip instruction.
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*/
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regs->cr_iip = next_ip;
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ia64_psr(regs)->ri = 0;
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return rv;
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}
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/*
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* BR[btype] = IP+16
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*/
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switch(btype) {
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case 0:
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regs->b0 = next_ip;
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break;
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case 1:
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rv.fkt = (unsigned long) &ia64_set_b1;
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break;
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case 2:
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rv.fkt = (unsigned long) &ia64_set_b2;
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break;
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case 3:
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rv.fkt = (unsigned long) &ia64_set_b3;
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break;
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case 4:
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rv.fkt = (unsigned long) &ia64_set_b4;
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break;
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case 5:
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rv.fkt = (unsigned long) &ia64_set_b5;
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break;
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case 6:
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regs->b6 = next_ip;
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break;
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case 7:
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regs->b7 = next_ip;
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break;
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}
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rv.arg1 = next_ip;
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/*
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* AR[PFS].pfm = CFM
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* AR[PFS].pec = AR[EC]
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* AR[PFS].ppl = PSR.cpl
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*/
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cpl = ia64_psr(regs)->cpl;
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regs->ar_pfs = ((regs->cr_ifs & 0x3fffffffff)
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| (ar_ec << 52) | (cpl << 62));
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/*
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* CFM.sof -= CFM.sol
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* CFM.sol = 0
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* CFM.sor = 0
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* CFM.rrb.gr = 0
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* CFM.rrb.fr = 0
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* CFM.rrb.pr = 0
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*/
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regs->cr_ifs = ((regs->cr_ifs & 0xffffffc00000007f)
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- ((regs->cr_ifs >> 7) & 0x7f));
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break;
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default:
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/*
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* Unknown opcode.
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*/
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return rv;
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}
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regs->cr_iip += offset;
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ia64_psr(regs)->ri = 0;
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if (ia64_psr(regs)->it == 0)
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unimplemented_address = unimplemented_physical_address(regs->cr_iip);
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else
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unimplemented_address = unimplemented_virtual_address(regs->cr_iip);
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if (unimplemented_address) {
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/*
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* The target address contains unimplemented bits.
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*/
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printk(KERN_DEBUG "Woah! Unimplemented Instruction Address Trap!\n");
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siginfo.si_signo = SIGILL;
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siginfo.si_errno = 0;
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siginfo.si_flags = 0;
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siginfo.si_isr = 0;
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siginfo.si_imm = 0;
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siginfo.si_code = ILL_BADIADDR;
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force_sig_info(SIGILL, &siginfo, current);
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} else if (ia64_psr(regs)->tb) {
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/*
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* Branch Tracing is enabled.
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* Force a taken branch signal.
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*/
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siginfo.si_signo = SIGTRAP;
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siginfo.si_errno = 0;
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siginfo.si_code = TRAP_BRANCH;
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siginfo.si_flags = 0;
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siginfo.si_isr = 0;
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siginfo.si_addr = 0;
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siginfo.si_imm = 0;
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force_sig_info(SIGTRAP, &siginfo, current);
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} else if (ia64_psr(regs)->ss) {
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/*
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* Single Step is enabled.
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* Force a trace signal.
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*/
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siginfo.si_signo = SIGTRAP;
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siginfo.si_errno = 0;
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siginfo.si_code = TRAP_TRACE;
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siginfo.si_flags = 0;
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siginfo.si_isr = 0;
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siginfo.si_addr = 0;
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siginfo.si_imm = 0;
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force_sig_info(SIGTRAP, &siginfo, current);
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}
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return rv;
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}
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