640 lines
14 KiB
C
640 lines
14 KiB
C
/*
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* vtlb.c: guest virtual tlb handling module.
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* Copyright (c) 2004, Intel Corporation.
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* Yaozu Dong (Eddie Dong) <Eddie.dong@intel.com>
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* Xuefei Xu (Anthony Xu) <anthony.xu@intel.com>
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*
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* Copyright (c) 2007, Intel Corporation.
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* Xuefei Xu (Anthony Xu) <anthony.xu@intel.com>
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include "vcpu.h"
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#include <linux/rwsem.h>
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#include <asm/tlb.h>
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/*
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* Check to see if the address rid:va is translated by the TLB
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*/
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static int __is_tr_translated(struct thash_data *trp, u64 rid, u64 va)
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{
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return ((trp->p) && (trp->rid == rid)
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&& ((va-trp->vadr) < PSIZE(trp->ps)));
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}
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/*
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* Only for GUEST TR format.
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*/
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static int __is_tr_overlap(struct thash_data *trp, u64 rid, u64 sva, u64 eva)
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{
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u64 sa1, ea1;
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if (!trp->p || trp->rid != rid)
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return 0;
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sa1 = trp->vadr;
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ea1 = sa1 + PSIZE(trp->ps) - 1;
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eva -= 1;
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if ((sva > ea1) || (sa1 > eva))
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return 0;
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else
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return 1;
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}
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void machine_tlb_purge(u64 va, u64 ps)
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{
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ia64_ptcl(va, ps << 2);
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}
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void local_flush_tlb_all(void)
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{
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int i, j;
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unsigned long flags, count0, count1;
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unsigned long stride0, stride1, addr;
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addr = current_vcpu->arch.ptce_base;
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count0 = current_vcpu->arch.ptce_count[0];
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count1 = current_vcpu->arch.ptce_count[1];
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stride0 = current_vcpu->arch.ptce_stride[0];
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stride1 = current_vcpu->arch.ptce_stride[1];
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local_irq_save(flags);
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for (i = 0; i < count0; ++i) {
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for (j = 0; j < count1; ++j) {
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ia64_ptce(addr);
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addr += stride1;
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}
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addr += stride0;
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}
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local_irq_restore(flags);
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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int vhpt_enabled(struct kvm_vcpu *vcpu, u64 vadr, enum vhpt_ref ref)
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{
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union ia64_rr vrr;
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union ia64_pta vpta;
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struct ia64_psr vpsr;
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vpsr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
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vrr.val = vcpu_get_rr(vcpu, vadr);
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vpta.val = vcpu_get_pta(vcpu);
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if (vrr.ve & vpta.ve) {
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switch (ref) {
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case DATA_REF:
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case NA_REF:
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return vpsr.dt;
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case INST_REF:
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return vpsr.dt && vpsr.it && vpsr.ic;
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case RSE_REF:
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return vpsr.dt && vpsr.rt;
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}
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}
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return 0;
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}
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struct thash_data *vsa_thash(union ia64_pta vpta, u64 va, u64 vrr, u64 *tag)
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{
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u64 index, pfn, rid, pfn_bits;
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pfn_bits = vpta.size - 5 - 8;
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pfn = REGION_OFFSET(va) >> _REGION_PAGE_SIZE(vrr);
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rid = _REGION_ID(vrr);
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index = ((rid & 0xff) << pfn_bits)|(pfn & ((1UL << pfn_bits) - 1));
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*tag = ((rid >> 8) & 0xffff) | ((pfn >> pfn_bits) << 16);
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return (struct thash_data *)((vpta.base << PTA_BASE_SHIFT) +
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(index << 5));
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}
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struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type)
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{
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struct thash_data *trp;
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int i;
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u64 rid;
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rid = vcpu_get_rr(vcpu, va);
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rid = rid & RR_RID_MASK;
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if (type == D_TLB) {
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if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) {
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for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0;
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i < NDTRS; i++, trp++) {
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if (__is_tr_translated(trp, rid, va))
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return trp;
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}
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}
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} else {
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if (vcpu_quick_region_check(vcpu->arch.itr_regions, va)) {
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for (trp = (struct thash_data *)&vcpu->arch.itrs, i = 0;
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i < NITRS; i++, trp++) {
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if (__is_tr_translated(trp, rid, va))
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return trp;
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}
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}
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}
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return NULL;
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}
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static void vhpt_insert(u64 pte, u64 itir, u64 ifa, u64 gpte)
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{
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union ia64_rr rr;
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struct thash_data *head;
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unsigned long ps, gpaddr;
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ps = itir_ps(itir);
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rr.val = ia64_get_rr(ifa);
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gpaddr = ((gpte & _PAGE_PPN_MASK) >> ps << ps) |
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(ifa & ((1UL << ps) - 1));
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head = (struct thash_data *)ia64_thash(ifa);
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head->etag = INVALID_TI_TAG;
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ia64_mf();
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head->page_flags = pte & ~PAGE_FLAGS_RV_MASK;
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head->itir = rr.ps << 2;
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head->etag = ia64_ttag(ifa);
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head->gpaddr = gpaddr;
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}
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void mark_pages_dirty(struct kvm_vcpu *v, u64 pte, u64 ps)
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{
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u64 i, dirty_pages = 1;
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u64 base_gfn = (pte&_PAGE_PPN_MASK) >> PAGE_SHIFT;
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vmm_spinlock_t *lock = __kvm_va(v->arch.dirty_log_lock_pa);
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void *dirty_bitmap = (void *)KVM_MEM_DIRTY_LOG_BASE;
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dirty_pages <<= ps <= PAGE_SHIFT ? 0 : ps - PAGE_SHIFT;
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vmm_spin_lock(lock);
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for (i = 0; i < dirty_pages; i++) {
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/* avoid RMW */
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if (!test_bit(base_gfn + i, dirty_bitmap))
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set_bit(base_gfn + i , dirty_bitmap);
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}
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vmm_spin_unlock(lock);
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}
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void thash_vhpt_insert(struct kvm_vcpu *v, u64 pte, u64 itir, u64 va, int type)
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{
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u64 phy_pte, psr;
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union ia64_rr mrr;
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mrr.val = ia64_get_rr(va);
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phy_pte = translate_phy_pte(&pte, itir, va);
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if (itir_ps(itir) >= mrr.ps) {
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vhpt_insert(phy_pte, itir, va, pte);
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} else {
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phy_pte &= ~PAGE_FLAGS_RV_MASK;
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psr = ia64_clear_ic();
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ia64_itc(type, va, phy_pte, itir_ps(itir));
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paravirt_dv_serialize_data();
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ia64_set_psr(psr);
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}
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if (!(pte&VTLB_PTE_IO))
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mark_pages_dirty(v, pte, itir_ps(itir));
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}
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/*
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* vhpt lookup
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*/
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struct thash_data *vhpt_lookup(u64 va)
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{
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struct thash_data *head;
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u64 tag;
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head = (struct thash_data *)ia64_thash(va);
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tag = ia64_ttag(va);
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if (head->etag == tag)
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return head;
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return NULL;
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}
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u64 guest_vhpt_lookup(u64 iha, u64 *pte)
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{
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u64 ret;
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struct thash_data *data;
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data = __vtr_lookup(current_vcpu, iha, D_TLB);
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if (data != NULL)
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thash_vhpt_insert(current_vcpu, data->page_flags,
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data->itir, iha, D_TLB);
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asm volatile ("rsm psr.ic|psr.i;;"
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"srlz.d;;"
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"ld8.s r9=[%1];;"
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"tnat.nz p6,p7=r9;;"
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"(p6) mov %0=1;"
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"(p6) mov r9=r0;"
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"(p7) extr.u r9=r9,0,53;;"
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"(p7) mov %0=r0;"
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"(p7) st8 [%2]=r9;;"
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"ssm psr.ic;;"
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"srlz.d;;"
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"ssm psr.i;;"
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"srlz.d;;"
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: "=&r"(ret) : "r"(iha), "r"(pte) : "memory");
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return ret;
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}
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/*
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* purge software guest tlb
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*/
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static void vtlb_purge(struct kvm_vcpu *v, u64 va, u64 ps)
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{
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struct thash_data *cur;
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u64 start, curadr, size, psbits, tag, rr_ps, num;
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union ia64_rr vrr;
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struct thash_cb *hcb = &v->arch.vtlb;
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vrr.val = vcpu_get_rr(v, va);
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psbits = VMX(v, psbits[(va >> 61)]);
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start = va & ~((1UL << ps) - 1);
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while (psbits) {
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curadr = start;
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rr_ps = __ffs(psbits);
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psbits &= ~(1UL << rr_ps);
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num = 1UL << ((ps < rr_ps) ? 0 : (ps - rr_ps));
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size = PSIZE(rr_ps);
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vrr.ps = rr_ps;
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while (num) {
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cur = vsa_thash(hcb->pta, curadr, vrr.val, &tag);
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if (cur->etag == tag && cur->ps == rr_ps)
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cur->etag = INVALID_TI_TAG;
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curadr += size;
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num--;
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}
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}
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}
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/*
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* purge VHPT and machine TLB
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*/
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static void vhpt_purge(struct kvm_vcpu *v, u64 va, u64 ps)
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{
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struct thash_data *cur;
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u64 start, size, tag, num;
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union ia64_rr rr;
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start = va & ~((1UL << ps) - 1);
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rr.val = ia64_get_rr(va);
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size = PSIZE(rr.ps);
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num = 1UL << ((ps < rr.ps) ? 0 : (ps - rr.ps));
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while (num) {
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cur = (struct thash_data *)ia64_thash(start);
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tag = ia64_ttag(start);
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if (cur->etag == tag)
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cur->etag = INVALID_TI_TAG;
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start += size;
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num--;
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}
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machine_tlb_purge(va, ps);
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}
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/*
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* Insert an entry into hash TLB or VHPT.
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* NOTES:
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* 1: When inserting VHPT to thash, "va" is a must covered
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* address by the inserted machine VHPT entry.
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* 2: The format of entry is always in TLB.
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* 3: The caller need to make sure the new entry will not overlap
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* with any existed entry.
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*/
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void vtlb_insert(struct kvm_vcpu *v, u64 pte, u64 itir, u64 va)
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{
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struct thash_data *head;
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union ia64_rr vrr;
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u64 tag;
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struct thash_cb *hcb = &v->arch.vtlb;
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vrr.val = vcpu_get_rr(v, va);
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vrr.ps = itir_ps(itir);
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VMX(v, psbits[va >> 61]) |= (1UL << vrr.ps);
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head = vsa_thash(hcb->pta, va, vrr.val, &tag);
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head->page_flags = pte;
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head->itir = itir;
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head->etag = tag;
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}
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int vtr_find_overlap(struct kvm_vcpu *vcpu, u64 va, u64 ps, int type)
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{
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struct thash_data *trp;
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int i;
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u64 end, rid;
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rid = vcpu_get_rr(vcpu, va);
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rid = rid & RR_RID_MASK;
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end = va + PSIZE(ps);
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if (type == D_TLB) {
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if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) {
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for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0;
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i < NDTRS; i++, trp++) {
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if (__is_tr_overlap(trp, rid, va, end))
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return i;
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}
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}
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} else {
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if (vcpu_quick_region_check(vcpu->arch.itr_regions, va)) {
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for (trp = (struct thash_data *)&vcpu->arch.itrs, i = 0;
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i < NITRS; i++, trp++) {
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if (__is_tr_overlap(trp, rid, va, end))
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return i;
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}
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}
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}
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return -1;
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}
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/*
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* Purge entries in VTLB and VHPT
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*/
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void thash_purge_entries(struct kvm_vcpu *v, u64 va, u64 ps)
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{
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if (vcpu_quick_region_check(v->arch.tc_regions, va))
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vtlb_purge(v, va, ps);
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vhpt_purge(v, va, ps);
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}
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void thash_purge_entries_remote(struct kvm_vcpu *v, u64 va, u64 ps)
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{
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u64 old_va = va;
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va = REGION_OFFSET(va);
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if (vcpu_quick_region_check(v->arch.tc_regions, old_va))
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vtlb_purge(v, va, ps);
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vhpt_purge(v, va, ps);
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}
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u64 translate_phy_pte(u64 *pte, u64 itir, u64 va)
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{
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u64 ps, ps_mask, paddr, maddr, io_mask;
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union pte_flags phy_pte;
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ps = itir_ps(itir);
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ps_mask = ~((1UL << ps) - 1);
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phy_pte.val = *pte;
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paddr = *pte;
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paddr = ((paddr & _PAGE_PPN_MASK) & ps_mask) | (va & ~ps_mask);
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maddr = kvm_get_mpt_entry(paddr >> PAGE_SHIFT);
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io_mask = maddr & GPFN_IO_MASK;
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if (io_mask && (io_mask != GPFN_PHYS_MMIO)) {
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*pte |= VTLB_PTE_IO;
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return -1;
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}
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maddr = ((maddr & _PAGE_PPN_MASK) & PAGE_MASK) |
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(paddr & ~PAGE_MASK);
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phy_pte.ppn = maddr >> ARCH_PAGE_SHIFT;
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return phy_pte.val;
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}
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/*
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* Purge overlap TCs and then insert the new entry to emulate itc ops.
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* Notes: Only TC entry can purge and insert.
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*/
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void thash_purge_and_insert(struct kvm_vcpu *v, u64 pte, u64 itir,
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u64 ifa, int type)
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{
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u64 ps;
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u64 phy_pte, io_mask, index;
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union ia64_rr vrr, mrr;
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ps = itir_ps(itir);
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vrr.val = vcpu_get_rr(v, ifa);
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mrr.val = ia64_get_rr(ifa);
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index = (pte & _PAGE_PPN_MASK) >> PAGE_SHIFT;
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io_mask = kvm_get_mpt_entry(index) & GPFN_IO_MASK;
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phy_pte = translate_phy_pte(&pte, itir, ifa);
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/* Ensure WB attribute if pte is related to a normal mem page,
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* which is required by vga acceleration since qemu maps shared
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* vram buffer with WB.
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*/
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if (!(pte & VTLB_PTE_IO) && ((pte & _PAGE_MA_MASK) != _PAGE_MA_NAT) &&
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io_mask != GPFN_PHYS_MMIO) {
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pte &= ~_PAGE_MA_MASK;
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phy_pte &= ~_PAGE_MA_MASK;
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}
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vtlb_purge(v, ifa, ps);
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vhpt_purge(v, ifa, ps);
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if ((ps != mrr.ps) || (pte & VTLB_PTE_IO)) {
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vtlb_insert(v, pte, itir, ifa);
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vcpu_quick_region_set(VMX(v, tc_regions), ifa);
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}
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if (pte & VTLB_PTE_IO)
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return;
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if (ps >= mrr.ps)
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vhpt_insert(phy_pte, itir, ifa, pte);
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else {
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u64 psr;
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phy_pte &= ~PAGE_FLAGS_RV_MASK;
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psr = ia64_clear_ic();
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ia64_itc(type, ifa, phy_pte, ps);
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paravirt_dv_serialize_data();
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ia64_set_psr(psr);
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}
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if (!(pte&VTLB_PTE_IO))
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mark_pages_dirty(v, pte, ps);
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}
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/*
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* Purge all TCs or VHPT entries including those in Hash table.
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*
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*/
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void thash_purge_all(struct kvm_vcpu *v)
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{
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int i;
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struct thash_data *head;
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struct thash_cb *vtlb, *vhpt;
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vtlb = &v->arch.vtlb;
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vhpt = &v->arch.vhpt;
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for (i = 0; i < 8; i++)
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VMX(v, psbits[i]) = 0;
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head = vtlb->hash;
|
|
for (i = 0; i < vtlb->num; i++) {
|
|
head->page_flags = 0;
|
|
head->etag = INVALID_TI_TAG;
|
|
head->itir = 0;
|
|
head->next = 0;
|
|
head++;
|
|
};
|
|
|
|
head = vhpt->hash;
|
|
for (i = 0; i < vhpt->num; i++) {
|
|
head->page_flags = 0;
|
|
head->etag = INVALID_TI_TAG;
|
|
head->itir = 0;
|
|
head->next = 0;
|
|
head++;
|
|
};
|
|
|
|
local_flush_tlb_all();
|
|
}
|
|
|
|
/*
|
|
* Lookup the hash table and its collision chain to find an entry
|
|
* covering this address rid:va or the entry.
|
|
*
|
|
* INPUT:
|
|
* in: TLB format for both VHPT & TLB.
|
|
*/
|
|
struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data)
|
|
{
|
|
struct thash_data *cch;
|
|
u64 psbits, ps, tag;
|
|
union ia64_rr vrr;
|
|
|
|
struct thash_cb *hcb = &v->arch.vtlb;
|
|
|
|
cch = __vtr_lookup(v, va, is_data);
|
|
if (cch)
|
|
return cch;
|
|
|
|
if (vcpu_quick_region_check(v->arch.tc_regions, va) == 0)
|
|
return NULL;
|
|
|
|
psbits = VMX(v, psbits[(va >> 61)]);
|
|
vrr.val = vcpu_get_rr(v, va);
|
|
while (psbits) {
|
|
ps = __ffs(psbits);
|
|
psbits &= ~(1UL << ps);
|
|
vrr.ps = ps;
|
|
cch = vsa_thash(hcb->pta, va, vrr.val, &tag);
|
|
if (cch->etag == tag && cch->ps == ps)
|
|
return cch;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Initialize internal control data before service.
|
|
*/
|
|
void thash_init(struct thash_cb *hcb, u64 sz)
|
|
{
|
|
int i;
|
|
struct thash_data *head;
|
|
|
|
hcb->pta.val = (unsigned long)hcb->hash;
|
|
hcb->pta.vf = 1;
|
|
hcb->pta.ve = 1;
|
|
hcb->pta.size = sz;
|
|
head = hcb->hash;
|
|
for (i = 0; i < hcb->num; i++) {
|
|
head->page_flags = 0;
|
|
head->itir = 0;
|
|
head->etag = INVALID_TI_TAG;
|
|
head->next = 0;
|
|
head++;
|
|
}
|
|
}
|
|
|
|
u64 kvm_get_mpt_entry(u64 gpfn)
|
|
{
|
|
u64 *base = (u64 *) KVM_P2M_BASE;
|
|
|
|
if (gpfn >= (KVM_P2M_SIZE >> 3))
|
|
panic_vm(current_vcpu, "Invalid gpfn =%lx\n", gpfn);
|
|
|
|
return *(base + gpfn);
|
|
}
|
|
|
|
u64 kvm_lookup_mpa(u64 gpfn)
|
|
{
|
|
u64 maddr;
|
|
maddr = kvm_get_mpt_entry(gpfn);
|
|
return maddr&_PAGE_PPN_MASK;
|
|
}
|
|
|
|
u64 kvm_gpa_to_mpa(u64 gpa)
|
|
{
|
|
u64 pte = kvm_lookup_mpa(gpa >> PAGE_SHIFT);
|
|
return (pte >> PAGE_SHIFT << PAGE_SHIFT) | (gpa & ~PAGE_MASK);
|
|
}
|
|
|
|
/*
|
|
* Fetch guest bundle code.
|
|
* INPUT:
|
|
* gip: guest ip
|
|
* pbundle: used to return fetched bundle.
|
|
*/
|
|
int fetch_code(struct kvm_vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle)
|
|
{
|
|
u64 gpip = 0; /* guest physical IP*/
|
|
u64 *vpa;
|
|
struct thash_data *tlb;
|
|
u64 maddr;
|
|
|
|
if (!(VCPU(vcpu, vpsr) & IA64_PSR_IT)) {
|
|
/* I-side physical mode */
|
|
gpip = gip;
|
|
} else {
|
|
tlb = vtlb_lookup(vcpu, gip, I_TLB);
|
|
if (tlb)
|
|
gpip = (tlb->ppn >> (tlb->ps - 12) << tlb->ps) |
|
|
(gip & (PSIZE(tlb->ps) - 1));
|
|
}
|
|
if (gpip) {
|
|
maddr = kvm_gpa_to_mpa(gpip);
|
|
} else {
|
|
tlb = vhpt_lookup(gip);
|
|
if (tlb == NULL) {
|
|
ia64_ptcl(gip, ARCH_PAGE_SHIFT << 2);
|
|
return IA64_FAULT;
|
|
}
|
|
maddr = (tlb->ppn >> (tlb->ps - 12) << tlb->ps)
|
|
| (gip & (PSIZE(tlb->ps) - 1));
|
|
}
|
|
vpa = (u64 *)__kvm_va(maddr);
|
|
|
|
pbundle->i64[0] = *vpa++;
|
|
pbundle->i64[1] = *vpa;
|
|
|
|
return IA64_NO_FAULT;
|
|
}
|
|
|
|
void kvm_init_vhpt(struct kvm_vcpu *v)
|
|
{
|
|
v->arch.vhpt.num = VHPT_NUM_ENTRIES;
|
|
thash_init(&v->arch.vhpt, VHPT_SHIFT);
|
|
ia64_set_pta(v->arch.vhpt.pta.val);
|
|
/*Enable VHPT here?*/
|
|
}
|
|
|
|
void kvm_init_vtlb(struct kvm_vcpu *v)
|
|
{
|
|
v->arch.vtlb.num = VTLB_NUM_ENTRIES;
|
|
thash_init(&v->arch.vtlb, VTLB_SHIFT);
|
|
}
|