389 lines
8.7 KiB
C
389 lines
8.7 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#include "common.h"
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/* does the board have sdram or ddram */
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static int dram_type;
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static struct ralink_pinmux_grp mode_mux[] = {
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{
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.name = "i2c",
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.mask = MT7620_GPIO_MODE_I2C,
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.gpio_first = 1,
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.gpio_last = 2,
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}, {
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.name = "spi",
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.mask = MT7620_GPIO_MODE_SPI,
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.gpio_first = 3,
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.gpio_last = 6,
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}, {
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.name = "uartlite",
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.mask = MT7620_GPIO_MODE_UART1,
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.gpio_first = 15,
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.gpio_last = 16,
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}, {
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.name = "wdt",
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.mask = MT7620_GPIO_MODE_WDT,
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.gpio_first = 17,
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.gpio_last = 17,
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}, {
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.name = "mdio",
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.mask = MT7620_GPIO_MODE_MDIO,
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.gpio_first = 22,
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.gpio_last = 23,
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}, {
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.name = "rgmii1",
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.mask = MT7620_GPIO_MODE_RGMII1,
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.gpio_first = 24,
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.gpio_last = 35,
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}, {
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.name = "spi refclk",
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.mask = MT7620_GPIO_MODE_SPI_REF_CLK,
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.gpio_first = 37,
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.gpio_last = 39,
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}, {
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.name = "jtag",
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.mask = MT7620_GPIO_MODE_JTAG,
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.gpio_first = 40,
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.gpio_last = 44,
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}, {
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/* shared lines with jtag */
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.name = "ephy",
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.mask = MT7620_GPIO_MODE_EPHY,
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.gpio_first = 40,
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.gpio_last = 44,
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}, {
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.name = "nand",
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.mask = MT7620_GPIO_MODE_JTAG,
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.gpio_first = 45,
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.gpio_last = 59,
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}, {
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.name = "rgmii2",
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.mask = MT7620_GPIO_MODE_RGMII2,
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.gpio_first = 60,
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.gpio_last = 71,
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}, {
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.name = "wled",
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.mask = MT7620_GPIO_MODE_WLED,
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.gpio_first = 72,
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.gpio_last = 72,
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}, {0}
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};
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static struct ralink_pinmux_grp uart_mux[] = {
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{
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.name = "uartf",
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.mask = MT7620_GPIO_MODE_UARTF,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "pcm uartf",
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.mask = MT7620_GPIO_MODE_PCM_UARTF,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "pcm i2s",
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.mask = MT7620_GPIO_MODE_PCM_I2S,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "i2s uartf",
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.mask = MT7620_GPIO_MODE_I2S_UARTF,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "pcm gpio",
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.mask = MT7620_GPIO_MODE_PCM_GPIO,
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.gpio_first = 11,
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.gpio_last = 14,
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}, {
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.name = "gpio uartf",
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.mask = MT7620_GPIO_MODE_GPIO_UARTF,
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.gpio_first = 7,
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.gpio_last = 10,
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}, {
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.name = "gpio i2s",
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.mask = MT7620_GPIO_MODE_GPIO_I2S,
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.gpio_first = 7,
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.gpio_last = 10,
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}, {
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.name = "gpio",
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.mask = MT7620_GPIO_MODE_GPIO,
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}, {0}
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};
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struct ralink_pinmux rt_gpio_pinmux = {
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.mode = mode_mux,
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.uart = uart_mux,
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.uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
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.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
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};
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static __init u32
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mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
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{
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u64 t;
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t = ref_rate;
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t *= mul;
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do_div(t, div);
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return t;
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}
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#define MHZ(x) ((x) * 1000 * 1000)
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static __init unsigned long
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mt7620_get_xtal_rate(void)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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if (reg & SYSCFG0_XTAL_FREQ_SEL)
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return MHZ(40);
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return MHZ(20);
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}
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static __init unsigned long
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mt7620_get_periph_rate(unsigned long xtal_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
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if (reg & CLKCFG0_PERI_CLK_SEL)
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return xtal_rate;
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return MHZ(40);
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}
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static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
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static __init unsigned long
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mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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if (reg & CPLL_CFG0_BYPASS_REF_CLK)
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return xtal_rate;
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if ((reg & CPLL_CFG0_SW_CFG) == 0)
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return MHZ(600);
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mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
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CPLL_CFG0_PLL_MULT_RATIO_MASK;
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mul += 24;
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if (reg & CPLL_CFG0_LC_CURFCK)
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mul *= 2;
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div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
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CPLL_CFG0_PLL_DIV_RATIO_MASK;
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WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
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return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
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}
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static __init unsigned long
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mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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if (reg & CPLL_CFG1_CPU_AUX1)
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return xtal_rate;
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if (reg & CPLL_CFG1_CPU_AUX0)
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return MHZ(480);
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return cpu_pll_rate;
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}
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static __init unsigned long
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mt7620_get_cpu_rate(unsigned long pll_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
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div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
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CPU_SYS_CLKCFG_CPU_FDIV_MASK;
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return mt7620_calc_rate(pll_rate, mul, div);
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}
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static const u32 mt7620_ocp_dividers[16] __initconst = {
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[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
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[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
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[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
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[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
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[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
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};
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static __init unsigned long
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mt7620_get_dram_rate(unsigned long pll_rate)
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{
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if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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return pll_rate / 4;
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return pll_rate / 3;
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}
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static __init unsigned long
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mt7620_get_sys_rate(unsigned long cpu_rate)
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{
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u32 reg;
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u32 ocp_ratio;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
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CPU_SYS_CLKCFG_OCP_RATIO_MASK;
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if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
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return cpu_rate;
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div = mt7620_ocp_dividers[ocp_ratio];
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if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
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return cpu_rate;
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return cpu_rate / div;
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}
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void __init ralink_clk_init(void)
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{
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unsigned long xtal_rate;
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unsigned long cpu_pll_rate;
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unsigned long pll_rate;
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unsigned long cpu_rate;
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unsigned long sys_rate;
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unsigned long dram_rate;
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unsigned long periph_rate;
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xtal_rate = mt7620_get_xtal_rate();
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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#define RFMT(label) label ":%lu.%03luMHz "
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
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RINT(cpu_rate), RFRAC(cpu_rate),
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RINT(dram_rate), RFRAC(dram_rate),
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RINT(sys_rate), RFRAC(sys_rate),
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RINT(periph_rate), RFRAC(periph_rate));
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#undef RFRAC
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#undef RINT
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#undef RFMT
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000500.uart", periph_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
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rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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u32 cfg0;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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} else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
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}
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_SDRAM:
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pr_info("Board has SDRAM\n");
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soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
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soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR1:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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soc_info->mem_base = MT7620_DRAM_BASE;
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}
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