555 lines
14 KiB
C
555 lines
14 KiB
C
/*
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* Toshiba RBTX4939 setup routines.
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* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/leds.h>
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#include <linux/interrupt.h>
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#include <linux/smc91x.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/map.h>
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#include <asm/reboot.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/rbtx4939.h>
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static void rbtx4939_machine_restart(char *command)
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{
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local_irq_disable();
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writeb(1, rbtx4939_reseten_addr);
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writeb(1, rbtx4939_softreset_addr);
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while (1)
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;
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}
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static void __init rbtx4939_time_init(void)
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{
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tx4939_time_init(0);
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}
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#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X)
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#define HAVE_RBTX4939_IOSWAB
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#define IS_CE1_ADDR(addr) \
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((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
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static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
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{
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return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
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}
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static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
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{
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return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
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}
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#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
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static void __init rbtx4939_pci_setup(void)
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{
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#ifdef CONFIG_PCI
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int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
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struct pci_controller *c = &txx9_primary_pcic;
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register_pci_controller(c);
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tx4939_report_pciclk();
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tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
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if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
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(__raw_readq(&tx4939_ccfgptr->pcfg) &
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(TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
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tx4939_report_pci1clk();
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/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
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c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
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register_pci_controller(c);
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tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
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}
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tx4939_setup_pcierr_irq();
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#endif /* CONFIG_PCI */
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}
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static unsigned long long default_ebccr[] __initdata = {
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0x01c0000000007608ULL, /* 64M ROM */
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0x017f000000007049ULL, /* 1M IOC */
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0x0180000000408608ULL, /* ISA */
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0,
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};
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static void __init rbtx4939_ebusc_setup(void)
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{
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int i;
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unsigned int sp;
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/* use user-configured speed */
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sp = TX4939_EBUSC_CR(0) & 0x30;
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default_ebccr[0] |= sp;
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default_ebccr[1] |= sp;
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default_ebccr[2] |= sp;
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/* initialise by myself */
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for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
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if (default_ebccr[i])
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____raw_writeq(default_ebccr[i],
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&tx4939_ebuscptr->cr[i]);
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else
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____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
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& ~8,
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&tx4939_ebuscptr->cr[i]);
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}
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}
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static void __init rbtx4939_update_ioc_pen(void)
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{
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__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
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__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
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__u8 pe1 = readb(rbtx4939_pe1_addr);
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__u8 pe2 = readb(rbtx4939_pe2_addr);
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__u8 pe3 = readb(rbtx4939_pe3_addr);
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if (pcfg & TX4939_PCFG_ATA0MODE)
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pe1 |= RBTX4939_PE1_ATA(0);
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else
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pe1 &= ~RBTX4939_PE1_ATA(0);
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if (pcfg & TX4939_PCFG_ATA1MODE) {
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pe1 |= RBTX4939_PE1_ATA(1);
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pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
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} else {
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pe1 &= ~RBTX4939_PE1_ATA(1);
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if (pcfg & TX4939_PCFG_ET0MODE)
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pe1 |= RBTX4939_PE1_RMII(0);
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else
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pe1 &= ~RBTX4939_PE1_RMII(0);
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if (pcfg & TX4939_PCFG_ET1MODE)
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pe1 |= RBTX4939_PE1_RMII(1);
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else
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pe1 &= ~RBTX4939_PE1_RMII(1);
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}
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if (ccfg & TX4939_CCFG_PTSEL)
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
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RBTX4939_PE3_VP_S);
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else {
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__u64 vmode = pcfg &
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(TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
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if (vmode == 0)
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
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RBTX4939_PE3_VP_S);
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else if (vmode == TX4939_PCFG_VPSMODE) {
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pe3 |= RBTX4939_PE3_VP_P;
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
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} else if (vmode == TX4939_PCFG_VSSMODE) {
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pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
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pe3 &= ~RBTX4939_PE3_VP_P;
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} else {
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pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
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pe3 &= ~RBTX4939_PE3_VP_S;
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}
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}
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if (pcfg & TX4939_PCFG_SPIMODE) {
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if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
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pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
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else {
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if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
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pe2 |= RBTX4939_PE2_SIO2;
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pe2 &= ~RBTX4939_PE2_SIO0;
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} else {
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pe2 |= RBTX4939_PE2_SIO0;
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pe2 &= ~RBTX4939_PE2_SIO2;
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}
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}
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if (pcfg & TX4939_PCFG_SIO3MODE)
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pe2 |= RBTX4939_PE2_SIO3;
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else
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pe2 &= ~RBTX4939_PE2_SIO3;
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pe2 &= ~RBTX4939_PE2_SPI;
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} else {
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pe2 |= RBTX4939_PE2_SPI;
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pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
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RBTX4939_PE2_SIO0);
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}
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if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
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pe2 |= RBTX4939_PE2_GPIO;
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else
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pe2 &= ~RBTX4939_PE2_GPIO;
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writeb(pe1, rbtx4939_pe1_addr);
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writeb(pe2, rbtx4939_pe2_addr);
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writeb(pe3, rbtx4939_pe3_addr);
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}
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#define RBTX4939_MAX_7SEGLEDS 8
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#if IS_ENABLED(CONFIG_LEDS_CLASS)
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static u8 led_val[RBTX4939_MAX_7SEGLEDS];
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struct rbtx4939_led_data {
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struct led_classdev cdev;
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char name[32];
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unsigned int num;
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};
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/* Use "dot" in 7seg LEDs */
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static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
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enum led_brightness value)
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{
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struct rbtx4939_led_data *led_dat =
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container_of(led_cdev, struct rbtx4939_led_data, cdev);
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unsigned int num = led_dat->num;
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unsigned long flags;
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local_irq_save(flags);
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led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
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writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
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local_irq_restore(flags);
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}
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static int __init rbtx4939_led_probe(struct platform_device *pdev)
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{
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struct rbtx4939_led_data *leds_data;
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int i;
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static char *default_triggers[] __initdata = {
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"heartbeat",
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"ide-disk",
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"nand-disk",
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};
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leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
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GFP_KERNEL);
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if (!leds_data)
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return -ENOMEM;
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for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
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int rc;
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struct rbtx4939_led_data *led_dat = &leds_data[i];
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led_dat->num = i;
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led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
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sprintf(led_dat->name, "rbtx4939:amber:%u", i);
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led_dat->cdev.name = led_dat->name;
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if (i < ARRAY_SIZE(default_triggers))
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led_dat->cdev.default_trigger = default_triggers[i];
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rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
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if (rc < 0)
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return rc;
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led_dat->cdev.brightness_set(&led_dat->cdev, 0);
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}
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return 0;
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}
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static struct platform_driver rbtx4939_led_driver = {
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.driver = {
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.name = "rbtx4939-led",
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.owner = THIS_MODULE,
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},
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};
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static void __init rbtx4939_led_setup(void)
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{
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platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
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platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
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}
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#else
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static inline void rbtx4939_led_setup(void)
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{
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}
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#endif
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static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
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{
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#if IS_ENABLED(CONFIG_LEDS_CLASS)
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unsigned long flags;
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local_irq_save(flags);
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/* bit7: reserved for LED class */
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led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
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val = led_val[pos];
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local_irq_restore(flags);
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#endif
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writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
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}
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static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
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{
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/* convert from map_to_seg7() notation */
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val = (val & 0x88) |
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((val & 0x40) >> 6) |
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((val & 0x20) >> 4) |
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((val & 0x10) >> 2) |
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((val & 0x04) << 2) |
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((val & 0x02) << 4) |
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((val & 0x01) << 6);
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__rbtx4939_7segled_putc(pos, val);
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}
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#if IS_ENABLED(CONFIG_MTD_RBTX4939)
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/* special mapping for boot rom */
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static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
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{
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u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
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unsigned char shift;
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if (bdipsw & 8) {
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/* BOOT Mode: USER ROM1 / USER ROM2 */
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shift = bdipsw & 3;
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/* rotate A[23:22] */
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return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22);
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}
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#ifdef __BIG_ENDIAN
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if (bdipsw == 0)
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/* BOOT Mode: Monitor ROM */
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ofs ^= 0x400000; /* swap A[22] */
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#endif
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return ofs;
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}
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static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs)
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{
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map_word r;
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ofs = rbtx4939_flash_fixup_ofs(ofs);
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r.x[0] = __raw_readw(map->virt + ofs);
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return r;
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}
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static void rbtx4939_flash_write16(struct map_info *map, const map_word datum,
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unsigned long ofs)
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{
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ofs = rbtx4939_flash_fixup_ofs(ofs);
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__raw_writew(datum.x[0], map->virt + ofs);
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mb(); /* see inline_map_write() in mtd/map.h */
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}
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static void rbtx4939_flash_copy_from(struct map_info *map, void *to,
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unsigned long from, ssize_t len)
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{
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u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
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unsigned char shift;
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ssize_t curlen;
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from += (unsigned long)map->virt;
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if (bdipsw & 8) {
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/* BOOT Mode: USER ROM1 / USER ROM2 */
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shift = bdipsw & 3;
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while (len) {
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curlen = min_t(unsigned long, len,
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0x400000 - (from & (0x400000 - 1)));
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memcpy(to,
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(void *)((from & ~0xc00000) |
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((((from >> 22) + shift) & 3) << 22)),
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curlen);
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len -= curlen;
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from += curlen;
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to += curlen;
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}
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return;
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}
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#ifdef __BIG_ENDIAN
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if (bdipsw == 0) {
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/* BOOT Mode: Monitor ROM */
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while (len) {
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curlen = min_t(unsigned long, len,
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0x400000 - (from & (0x400000 - 1)));
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memcpy(to, (void *)(from ^ 0x400000), curlen);
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len -= curlen;
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from += curlen;
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to += curlen;
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}
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return;
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}
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#endif
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memcpy(to, (void *)from, len);
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}
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static void rbtx4939_flash_map_init(struct map_info *map)
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{
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map->read = rbtx4939_flash_read16;
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map->write = rbtx4939_flash_write16;
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map->copy_from = rbtx4939_flash_copy_from;
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}
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static void __init rbtx4939_mtd_init(void)
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{
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static struct {
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struct platform_device dev;
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struct resource res;
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struct rbtx4939_flash_data data;
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} pdevs[4];
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int i;
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static char names[4][8];
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static struct mtd_partition parts[4];
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struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data;
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u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
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if (bdipsw & 8) {
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/* BOOT Mode: USER ROM1 / USER ROM2 */
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boot_pdata->nr_parts = 4;
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for (i = 0; i < boot_pdata->nr_parts; i++) {
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sprintf(names[i], "img%d", 4 - i);
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parts[i].name = names[i];
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parts[i].size = 0x400000;
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parts[i].offset = MTDPART_OFS_NXTBLK;
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}
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} else if (bdipsw == 0) {
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/* BOOT Mode: Monitor ROM */
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boot_pdata->nr_parts = 2;
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strcpy(names[0], "big");
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strcpy(names[1], "little");
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for (i = 0; i < boot_pdata->nr_parts; i++) {
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parts[i].name = names[i];
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parts[i].size = 0x400000;
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parts[i].offset = MTDPART_OFS_NXTBLK;
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}
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} else {
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/* BOOT Mode: ROM Emulator */
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boot_pdata->nr_parts = 2;
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parts[0].name = "boot";
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parts[0].offset = 0xc00000;
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parts[0].size = 0x400000;
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parts[1].name = "user";
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parts[1].offset = 0;
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parts[1].size = 0xc00000;
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}
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boot_pdata->parts = parts;
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boot_pdata->map_init = rbtx4939_flash_map_init;
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for (i = 0; i < ARRAY_SIZE(pdevs); i++) {
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struct resource *r = &pdevs[i].res;
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struct platform_device *dev = &pdevs[i].dev;
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r->start = 0x1f000000 - i * 0x1000000;
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r->end = r->start + 0x1000000 - 1;
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r->flags = IORESOURCE_MEM;
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pdevs[i].data.width = 2;
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dev->num_resources = 1;
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dev->resource = r;
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dev->id = i;
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dev->name = "rbtx4939-flash";
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dev->dev.platform_data = &pdevs[i].data;
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platform_device_register(dev);
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}
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}
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#else
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static void __init rbtx4939_mtd_init(void)
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{
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}
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#endif
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static void __init rbtx4939_arch_init(void)
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{
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rbtx4939_pci_setup();
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}
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static void __init rbtx4939_device_init(void)
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{
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unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
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struct resource smc_res[] = {
|
|
{
|
|
.start = smc_addr,
|
|
.end = smc_addr + 0x10 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = RBTX4939_IRQ_ETHER,
|
|
/* override default irq flag defined in smc91x.h */
|
|
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
|
},
|
|
};
|
|
struct smc91x_platdata smc_pdata = {
|
|
.flags = SMC91X_USE_16BIT,
|
|
};
|
|
struct platform_device *pdev;
|
|
#if IS_ENABLED(CONFIG_TC35815)
|
|
int i, j;
|
|
unsigned char ethaddr[2][6];
|
|
u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
|
|
if (bdipsw == 0)
|
|
memcpy(ethaddr[i], (void *)area, 6);
|
|
else {
|
|
u16 buf[3];
|
|
if (bdipsw & 8)
|
|
area -= 0x03000000;
|
|
else
|
|
area -= 0x01000000;
|
|
for (j = 0; j < 3; j++)
|
|
buf[j] = le16_to_cpup((u16 *)(area + j * 2));
|
|
memcpy(ethaddr[i], buf, 6);
|
|
}
|
|
}
|
|
tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
|
|
#endif
|
|
pdev = platform_device_alloc("smc91x", -1);
|
|
if (!pdev ||
|
|
platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
|
|
platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
|
|
platform_device_add(pdev))
|
|
platform_device_put(pdev);
|
|
rbtx4939_mtd_init();
|
|
/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
|
|
tx4939_ndfmc_init(10, 35,
|
|
(1 << 1) | (1 << 2),
|
|
(1 << 2)); /* ch1:8bit, ch2:16bit */
|
|
rbtx4939_led_setup();
|
|
tx4939_wdt_init();
|
|
tx4939_ata_init();
|
|
tx4939_rtc_init();
|
|
tx4939_dmac_init(0, 2);
|
|
tx4939_aclc_init();
|
|
platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
|
|
tx4939_sramc_init();
|
|
tx4939_rng_init();
|
|
}
|
|
|
|
static void __init rbtx4939_setup(void)
|
|
{
|
|
int i;
|
|
|
|
rbtx4939_ebusc_setup();
|
|
/* always enable ATA0 */
|
|
txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
|
|
if (txx9_master_clock == 0)
|
|
txx9_master_clock = 20000000;
|
|
tx4939_setup();
|
|
rbtx4939_update_ioc_pen();
|
|
#ifdef HAVE_RBTX4939_IOSWAB
|
|
ioswabw = rbtx4939_ioswabw;
|
|
__mem_ioswabw = rbtx4939_mem_ioswabw;
|
|
#endif
|
|
|
|
_machine_restart = rbtx4939_machine_restart;
|
|
|
|
txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
|
|
for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
|
|
txx9_7segled_putc(i, '-');
|
|
pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
|
|
readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
|
|
readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
|
|
|
|
#ifdef CONFIG_PCI
|
|
txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
|
|
txx9_board_pcibios_setup = tx4927_pcibios_setup;
|
|
#else
|
|
set_io_port_base(RBTX4939_ETHER_BASE);
|
|
#endif
|
|
|
|
tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
|
|
}
|
|
|
|
struct txx9_board_vec rbtx4939_vec __initdata = {
|
|
.system = "Toshiba RBTX4939",
|
|
.prom_init = rbtx4939_prom_init,
|
|
.mem_setup = rbtx4939_setup,
|
|
.irq_setup = rbtx4939_irq_setup,
|
|
.time_init = rbtx4939_time_init,
|
|
.device_init = rbtx4939_device_init,
|
|
.arch_init = rbtx4939_arch_init,
|
|
#ifdef CONFIG_PCI
|
|
.pci_map_irq = tx4939_pci_map_irq,
|
|
#endif
|
|
};
|