216 lines
5 KiB
C
216 lines
5 KiB
C
#ifndef _ASM_POWERPC_HUGETLB_H
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#define _ASM_POWERPC_HUGETLB_H
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#ifdef CONFIG_HUGETLB_PAGE
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#include <asm/page.h>
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#include <asm-generic/hugetlb.h>
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extern struct kmem_cache *hugepte_cache;
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* This should work for other subarchs too. But right now we use the
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* new format only for 64bit book3s
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*/
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static inline pte_t *hugepd_page(hugepd_t hpd)
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{
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BUG_ON(!hugepd_ok(hpd));
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/*
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* We have only four bits to encode, MMU page size
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*/
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BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf);
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return (pte_t *)(hpd.pd & ~HUGEPD_SHIFT_MASK);
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}
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static inline unsigned int hugepd_mmu_psize(hugepd_t hpd)
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{
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return (hpd.pd & HUGEPD_SHIFT_MASK) >> 2;
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}
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static inline unsigned int hugepd_shift(hugepd_t hpd)
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{
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return mmu_psize_to_shift(hugepd_mmu_psize(hpd));
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}
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#else
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static inline pte_t *hugepd_page(hugepd_t hpd)
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{
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BUG_ON(!hugepd_ok(hpd));
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return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
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}
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static inline unsigned int hugepd_shift(hugepd_t hpd)
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{
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return hpd.pd & HUGEPD_SHIFT_MASK;
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}
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#endif /* CONFIG_PPC_BOOK3S_64 */
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static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
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unsigned pdshift)
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{
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/*
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* On FSL BookE, we have multiple higher-level table entries that
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* point to the same hugepte. Just use the first one since they're all
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* identical. So for that case, idx=0.
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*/
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unsigned long idx = 0;
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pte_t *dir = hugepd_page(*hpdp);
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#ifndef CONFIG_PPC_FSL_BOOK3E
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idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
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#endif
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return dir + idx;
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}
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pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
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unsigned long addr, unsigned *shift);
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void flush_dcache_icache_hugepage(struct page *page);
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#if defined(CONFIG_PPC_MM_SLICES)
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int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
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unsigned long len);
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#else
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static inline int is_hugepage_only_range(struct mm_struct *mm,
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unsigned long addr,
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unsigned long len)
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{
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return 0;
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}
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#endif
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void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
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pte_t pte);
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void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
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unsigned long end, unsigned long floor,
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unsigned long ceiling);
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/*
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* The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs
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* to override the version in mm/hugetlb.c
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*/
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#define vma_mmu_pagesize vma_mmu_pagesize
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/*
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* If the arch doesn't supply something else, assume that hugepage
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* size aligned regions are ok without further preparation.
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*/
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static inline int prepare_hugepage_range(struct file *file,
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unsigned long addr, unsigned long len)
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{
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struct hstate *h = hstate_file(file);
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if (len & ~huge_page_mask(h))
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return -EINVAL;
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if (addr & ~huge_page_mask(h))
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return -EINVAL;
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return 0;
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}
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static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
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{
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}
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static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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set_pte_at(mm, addr, ptep, pte);
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}
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static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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#ifdef CONFIG_PPC64
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return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
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#else
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return __pte(pte_update(ptep, ~0UL, 0));
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#endif
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}
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static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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pte_t pte;
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pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
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flush_tlb_page(vma, addr);
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}
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static inline int huge_pte_none(pte_t pte)
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{
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return pte_none(pte);
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}
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static inline pte_t huge_pte_wrprotect(pte_t pte)
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{
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return pte_wrprotect(pte);
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}
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static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t pte, int dirty)
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{
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#ifdef HUGETLB_NEED_PRELOAD
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/*
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* The "return 1" forces a call of update_mmu_cache, which will write a
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* TLB entry. Without this, platforms that don't do a write of the TLB
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* entry in the TLB miss handler asm will fault ad infinitum.
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*/
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ptep_set_access_flags(vma, addr, ptep, pte, dirty);
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return 1;
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#else
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return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
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#endif
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}
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static inline pte_t huge_ptep_get(pte_t *ptep)
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{
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return *ptep;
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}
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static inline int arch_prepare_hugepage(struct page *page)
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{
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return 0;
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}
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static inline void arch_release_hugepage(struct page *page)
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{
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}
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static inline void arch_clear_hugepage_flags(struct page *page)
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{
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}
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#else /* ! CONFIG_HUGETLB_PAGE */
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static inline void flush_hugetlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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#define hugepd_shift(x) 0
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static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
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unsigned pdshift)
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{
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return 0;
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}
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#endif /* CONFIG_HUGETLB_PAGE */
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/*
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* FSL Book3E platforms require special gpage handling - the gpages
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* are reserved early in the boot process by memblock instead of via
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* the .dts as on IBM platforms.
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*/
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#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
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extern void __init reserve_hugetlb_gpages(void);
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#else
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static inline void reserve_hugetlb_gpages(void)
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{
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}
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#endif
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#endif /* _ASM_POWERPC_HUGETLB_H */
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