152 lines
5.5 KiB
C
152 lines
5.5 KiB
C
#ifndef _ASM_POWERPC_MMU_44X_H_
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#define _ASM_POWERPC_MMU_44X_H_
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/*
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* PPC440 support
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*/
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#include <asm/page.h>
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#define PPC44x_MMUCR_TID 0x000000ff
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#define PPC44x_MMUCR_STS 0x00010000
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#define PPC44x_TLB_PAGEID 0
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#define PPC44x_TLB_XLAT 1
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#define PPC44x_TLB_ATTRIB 2
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/* Page identification fields */
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#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
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#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
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#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
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#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
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#define PPC44x_TLB_4K 0x00000010
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#define PPC44x_TLB_16K 0x00000020
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#define PPC44x_TLB_64K 0x00000030
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#define PPC44x_TLB_256K 0x00000040
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#define PPC44x_TLB_1M 0x00000050
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#define PPC44x_TLB_16M 0x00000070
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#define PPC44x_TLB_256M 0x00000090
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/* Translation fields */
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#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
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#define PPC44x_TLB_ERPN_MASK 0x0000000f
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/* Storage attribute and access control fields */
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#define PPC44x_TLB_ATTR_MASK 0x0000ff80
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#define PPC44x_TLB_U0 0x00008000 /* User 0 */
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#define PPC44x_TLB_U1 0x00004000 /* User 1 */
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#define PPC44x_TLB_U2 0x00002000 /* User 2 */
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#define PPC44x_TLB_U3 0x00001000 /* User 3 */
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#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
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#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
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#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
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#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
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#define PPC44x_TLB_E 0x00000080 /* Memory is little endian */
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#define PPC44x_TLB_PERM_MASK 0x0000003f
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#define PPC44x_TLB_UX 0x00000020 /* User execution */
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#define PPC44x_TLB_UW 0x00000010 /* User write */
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#define PPC44x_TLB_UR 0x00000008 /* User read */
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#define PPC44x_TLB_SX 0x00000004 /* Super execution */
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#define PPC44x_TLB_SW 0x00000002 /* Super write */
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#define PPC44x_TLB_SR 0x00000001 /* Super read */
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/* Number of TLB entries */
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#define PPC44x_TLB_SIZE 64
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/* 47x bits */
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#define PPC47x_MMUCR_TID 0x0000ffff
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#define PPC47x_MMUCR_STS 0x00010000
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/* Page identification fields */
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#define PPC47x_TLB0_EPN_MASK 0xfffff000 /* Effective Page Number */
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#define PPC47x_TLB0_VALID 0x00000800 /* Valid flag */
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#define PPC47x_TLB0_TS 0x00000400 /* Translation address space */
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#define PPC47x_TLB0_4K 0x00000000
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#define PPC47x_TLB0_16K 0x00000010
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#define PPC47x_TLB0_64K 0x00000030
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#define PPC47x_TLB0_1M 0x00000070
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#define PPC47x_TLB0_16M 0x000000f0
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#define PPC47x_TLB0_256M 0x000001f0
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#define PPC47x_TLB0_1G 0x000003f0
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#define PPC47x_TLB0_BOLTED_R 0x00000008 /* tlbre only */
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/* Translation fields */
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#define PPC47x_TLB1_RPN_MASK 0xfffff000 /* Real Page Number */
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#define PPC47x_TLB1_ERPN_MASK 0x000003ff
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/* Storage attribute and access control fields */
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#define PPC47x_TLB2_ATTR_MASK 0x0003ff80
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#define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */
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#define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */
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#define PPC47x_TLB2_U0 0x00008000 /* User 0 */
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#define PPC47x_TLB2_U1 0x00004000 /* User 1 */
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#define PPC47x_TLB2_U2 0x00002000 /* User 2 */
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#define PPC47x_TLB2_U3 0x00001000 /* User 3 */
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#define PPC47x_TLB2_W 0x00000800 /* Caching is write-through */
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#define PPC47x_TLB2_I 0x00000400 /* Caching is inhibited */
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#define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */
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#define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */
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#define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */
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#define PPC47x_TLB2_PERM_MASK 0x0000003f
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#define PPC47x_TLB2_UX 0x00000020 /* User execution */
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#define PPC47x_TLB2_UW 0x00000010 /* User write */
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#define PPC47x_TLB2_UR 0x00000008 /* User read */
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#define PPC47x_TLB2_SX 0x00000004 /* Super execution */
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#define PPC47x_TLB2_SW 0x00000002 /* Super write */
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#define PPC47x_TLB2_SR 0x00000001 /* Super read */
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#define PPC47x_TLB2_U_RWX (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
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#define PPC47x_TLB2_S_RWX (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
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#define PPC47x_TLB2_S_RW (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
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#define PPC47x_TLB2_IMG (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
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#ifndef __ASSEMBLY__
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extern unsigned int tlb_44x_hwater;
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extern unsigned int tlb_44x_index;
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typedef struct {
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unsigned int id;
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unsigned int active;
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unsigned long vdso_base;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#ifndef CONFIG_PPC_EARLY_DEBUG_44x
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#define PPC44x_EARLY_TLBS 1
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#else
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#define PPC44x_EARLY_TLBS 2
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#define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \
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| (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
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#endif
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/* Size of the TLBs used for pinning in lowmem */
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#define PPC_PIN_SIZE (1 << 28) /* 256M */
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#if (PAGE_SHIFT == 12)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_4K
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#define PPC47x_TLBE_SIZE PPC47x_TLB0_4K
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#define mmu_virtual_psize MMU_PAGE_4K
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#elif (PAGE_SHIFT == 14)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
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#define PPC47x_TLBE_SIZE PPC47x_TLB0_16K
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#define mmu_virtual_psize MMU_PAGE_16K
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#elif (PAGE_SHIFT == 16)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
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#define PPC47x_TLBE_SIZE PPC47x_TLB0_64K
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#define mmu_virtual_psize MMU_PAGE_64K
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#elif (PAGE_SHIFT == 18)
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#define PPC44x_TLBE_SIZE PPC44x_TLB_256K
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#define mmu_virtual_psize MMU_PAGE_256K
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#else
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#error "Unsupported PAGE_SIZE"
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#endif
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#define mmu_linear_psize MMU_PAGE_256M
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#define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2)
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#define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
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#define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
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#define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT)
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#endif /* _ASM_POWERPC_MMU_44X_H_ */
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