196 lines
5.1 KiB
C
196 lines
5.1 KiB
C
/*
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* PQ2FADS board support
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Loosely based on mp82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/fsl_devices.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/cpm2.h>
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#include <asm/udbg.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/cpm2_pic.h>
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#include "pq2ads.h"
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#include "pq2.h"
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static void __init pq2fads_pic_init(void)
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{
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struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
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if (!np) {
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printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
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return;
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}
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cpm2_pic_init(np);
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of_node_put(np);
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/* Initialize stuff for the 82xx CPLD IC and install demux */
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pq2ads_pci_init_irq();
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}
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struct cpm_pin {
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int port, pin, flags;
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};
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static struct cpm_pin pq2fads_pins[] = {
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/* SCC1 */
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{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* SCC2 */
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{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC2 */
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{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC3 */
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{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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};
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static void __init init_ioports(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pq2fads_pins); i++) {
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struct cpm_pin *pin = &pq2fads_pins[i];
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cpm2_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
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}
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static void __init pq2fads_setup_arch(void)
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{
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struct device_node *np;
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__be32 __iomem *bcsr;
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if (ppc_md.progress)
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ppc_md.progress("pq2fads_setup_arch()", 0);
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cpm2_reset();
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np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr");
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if (!np) {
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printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n");
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return;
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}
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bcsr = of_iomap(np, 0);
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of_node_put(np);
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if (!bcsr) {
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printk(KERN_ERR "Cannot map BCSR registers\n");
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return;
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}
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/* Enable the serial and ethernet ports */
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clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
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setbits32(&bcsr[1], BCSR1_FETH_RST);
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clrbits32(&bcsr[3], BCSR3_FETHIEN2);
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setbits32(&bcsr[3], BCSR3_FETH2_RST);
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iounmap(bcsr);
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init_ioports();
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/* Enable external IRQs */
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clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
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pq2_init_pci();
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if (ppc_md.progress)
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ppc_md.progress("pq2fads_setup_arch(), finish", 0);
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init pq2fads_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,pq2fads");
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}
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static const struct of_device_id of_bus_ids[] __initconst = {
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{ .name = "soc", },
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{ .name = "cpm", },
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{ .name = "localbus", },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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machine_device_initcall(pq2fads, declare_of_platform_devices);
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define_machine(pq2fads)
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{
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.name = "Freescale PQ2FADS",
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.probe = pq2fads_probe,
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.setup_arch = pq2fads_setup_arch,
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.init_IRQ = pq2fads_pic_init,
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.get_irq = cpm2_get_irq,
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.calibrate_decr = generic_calibrate_decr,
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.restart = pq2_restart,
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.progress = udbg_progress,
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};
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