265 lines
7.2 KiB
C
265 lines
7.2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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#include "nv50_display.h"
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u64
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nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
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{
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struct nv84_fence_chan *fctx = chan->fence;
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return fctx->dispc_vma[crtc].offset;
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}
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static int
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nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
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int ret = RING_SPACE(chan, 8);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, chan->vram.handle);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
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OUT_RING (chan, upper_32_bits(virtual));
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OUT_RING (chan, lower_32_bits(virtual));
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OUT_RING (chan, sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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OUT_RING (chan, 0x00000000);
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FIRE_RING (chan);
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}
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return ret;
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}
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static int
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nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
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int ret = RING_SPACE(chan, 7);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, chan->vram.handle);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(virtual));
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OUT_RING (chan, lower_32_bits(virtual));
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OUT_RING (chan, sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
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FIRE_RING (chan);
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}
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return ret;
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}
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static int
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nv84_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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struct nv84_fence_chan *fctx = chan->fence;
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u64 addr = chan->chid * 16;
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if (fence->sysmem)
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addr += fctx->vma_gart.offset;
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else
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addr += fctx->vma.offset;
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return fctx->base.emit32(chan, addr, fence->base.seqno);
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}
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static int
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nv84_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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struct nv84_fence_chan *fctx = chan->fence;
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u64 addr = prev->chid * 16;
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if (fence->sysmem)
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addr += fctx->vma_gart.offset;
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else
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addr += fctx->vma.offset;
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return fctx->base.sync32(chan, addr, fence->base.seqno);
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}
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static u32
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nv84_fence_read(struct nouveau_channel *chan)
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{
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struct nv84_fence_priv *priv = chan->drm->fence;
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return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
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}
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static void
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nv84_fence_context_del(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->drm->dev;
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struct nv84_fence_priv *priv = chan->drm->fence;
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struct nv84_fence_chan *fctx = chan->fence;
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int i;
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for (i = 0; i < dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
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nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
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}
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nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
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nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
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nouveau_bo_vma_del(priv->bo, &fctx->vma);
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nouveau_fence_context_del(&fctx->base);
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chan->fence = NULL;
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nouveau_fence_context_free(&fctx->base);
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}
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int
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nv84_fence_context_new(struct nouveau_channel *chan)
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{
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struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
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struct nv84_fence_priv *priv = chan->drm->fence;
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struct nv84_fence_chan *fctx;
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int ret, i;
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fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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nouveau_fence_context_new(chan, &fctx->base);
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fctx->base.emit = nv84_fence_emit;
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fctx->base.sync = nv84_fence_sync;
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fctx->base.read = nv84_fence_read;
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fctx->base.emit32 = nv84_fence_emit32;
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fctx->base.sync32 = nv84_fence_sync32;
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fctx->base.sequence = nv84_fence_read(chan);
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ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
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if (ret == 0) {
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ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
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&fctx->vma_gart);
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}
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/* map display semaphore buffers into channel's vm */
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for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
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ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
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}
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if (ret)
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nv84_fence_context_del(chan);
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return ret;
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}
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static bool
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nv84_fence_suspend(struct nouveau_drm *drm)
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{
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struct nv84_fence_priv *priv = drm->fence;
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int i;
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priv->suspend = vmalloc(priv->base.contexts * sizeof(u32));
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if (priv->suspend) {
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for (i = 0; i < priv->base.contexts; i++)
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priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
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}
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return priv->suspend != NULL;
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}
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static void
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nv84_fence_resume(struct nouveau_drm *drm)
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{
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struct nv84_fence_priv *priv = drm->fence;
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int i;
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if (priv->suspend) {
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for (i = 0; i < priv->base.contexts; i++)
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nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
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vfree(priv->suspend);
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priv->suspend = NULL;
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}
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}
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static void
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nv84_fence_destroy(struct nouveau_drm *drm)
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{
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struct nv84_fence_priv *priv = drm->fence;
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nouveau_bo_unmap(priv->bo_gart);
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if (priv->bo_gart)
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nouveau_bo_unpin(priv->bo_gart);
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nouveau_bo_ref(NULL, &priv->bo_gart);
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nouveau_bo_unmap(priv->bo);
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if (priv->bo)
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nouveau_bo_unpin(priv->bo);
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nouveau_bo_ref(NULL, &priv->bo);
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drm->fence = NULL;
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kfree(priv);
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}
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int
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nv84_fence_create(struct nouveau_drm *drm)
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{
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struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device);
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struct nv84_fence_priv *priv;
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int ret;
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.dtor = nv84_fence_destroy;
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priv->base.suspend = nv84_fence_suspend;
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priv->base.resume = nv84_fence_resume;
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priv->base.context_new = nv84_fence_context_new;
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priv->base.context_del = nv84_fence_context_del;
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priv->base.contexts = pfifo->max + 1;
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priv->base.context_base = fence_context_alloc(priv->base.contexts);
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priv->base.uevent = true;
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ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
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TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo);
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if (ret == 0) {
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ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
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if (ret == 0) {
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ret = nouveau_bo_map(priv->bo);
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if (ret)
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nouveau_bo_unpin(priv->bo);
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}
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if (ret)
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nouveau_bo_ref(NULL, &priv->bo);
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}
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if (ret == 0)
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ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
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TTM_PL_FLAG_TT, 0, 0, NULL, NULL,
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&priv->bo_gart);
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if (ret == 0) {
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ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
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if (ret == 0) {
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ret = nouveau_bo_map(priv->bo_gart);
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if (ret)
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nouveau_bo_unpin(priv->bo_gart);
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}
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if (ret)
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nouveau_bo_ref(NULL, &priv->bo_gart);
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}
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if (ret)
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nv84_fence_destroy(drm);
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return ret;
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}
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