764 lines
22 KiB
C
764 lines
22 KiB
C
/*
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* Copyright (C) 2012 Mentor Graphics Inc.
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* Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/types.h>
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#include <linux/bitrev.h>
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#include <linux/io.h>
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#include <drm/drm_fourcc.h>
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#include "ipu-prv.h"
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struct ipu_cpmem_word {
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u32 data[5];
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u32 res[3];
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};
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struct ipu_ch_param {
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struct ipu_cpmem_word word[2];
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};
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struct ipu_cpmem {
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struct ipu_ch_param __iomem *base;
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u32 module;
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spinlock_t lock;
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int use_count;
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struct ipu_soc *ipu;
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};
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#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
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#define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
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#define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
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#define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
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#define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
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#define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
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#define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
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#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
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#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
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#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
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#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
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#define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
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#define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
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#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
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#define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
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#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
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#define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
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#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
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#define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
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#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
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#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
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#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
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#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
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#define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
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#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
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#define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
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#define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
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#define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
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#define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
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#define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3)
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#define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
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#define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
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#define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
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#define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
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#define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
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#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
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#define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
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#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
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#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
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#define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
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#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
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#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
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#define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
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#define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
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#define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
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#define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
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#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
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#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
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#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
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#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
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#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
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#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
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#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
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#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
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#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
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#define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
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#define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
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#define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
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static inline struct ipu_ch_param __iomem *
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ipu_get_cpmem(struct ipuv3_channel *ch)
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{
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struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
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return cpmem->base + ch->num;
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}
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static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
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{
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struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
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u32 bit = (wbs >> 8) % 160;
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u32 size = wbs & 0xff;
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u32 word = (wbs >> 8) / 160;
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u32 i = bit / 32;
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u32 ofs = bit % 32;
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u32 mask = (1 << size) - 1;
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u32 val;
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pr_debug("%s %d %d %d\n", __func__, word, bit , size);
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val = readl(&base->word[word].data[i]);
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val &= ~(mask << ofs);
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val |= v << ofs;
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writel(val, &base->word[word].data[i]);
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if ((bit + size - 1) / 32 > i) {
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val = readl(&base->word[word].data[i + 1]);
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val &= ~(mask >> (ofs ? (32 - ofs) : 0));
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val |= v >> (ofs ? (32 - ofs) : 0);
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writel(val, &base->word[word].data[i + 1]);
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}
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}
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static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
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{
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struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
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u32 bit = (wbs >> 8) % 160;
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u32 size = wbs & 0xff;
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u32 word = (wbs >> 8) / 160;
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u32 i = bit / 32;
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u32 ofs = bit % 32;
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u32 mask = (1 << size) - 1;
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u32 val = 0;
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pr_debug("%s %d %d %d\n", __func__, word, bit , size);
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val = (readl(&base->word[word].data[i]) >> ofs) & mask;
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if ((bit + size - 1) / 32 > i) {
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u32 tmp;
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tmp = readl(&base->word[word].data[i + 1]);
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tmp &= mask >> (ofs ? (32 - ofs) : 0);
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val |= tmp << (ofs ? (32 - ofs) : 0);
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}
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return val;
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}
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/*
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* The V4L2 spec defines packed RGB formats in memory byte order, which from
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* point of view of the IPU corresponds to little-endian words with the first
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* component in the least significant bits.
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* The DRM pixel formats and IPU internal representation are ordered the other
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* way around, with the first named component ordered at the most significant
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* bits. Further, V4L2 formats are not well defined:
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* http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
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* We choose the interpretation which matches GStreamer behavior.
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*/
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static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
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{
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switch (pixelformat) {
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case V4L2_PIX_FMT_RGB565:
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/*
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* Here we choose the 'corrected' interpretation of RGBP, a
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* little-endian 16-bit word with the red component at the most
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* significant bits:
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* g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
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*/
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return DRM_FORMAT_RGB565;
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case V4L2_PIX_FMT_BGR24:
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/* B G R <=> [24:0] R:G:B */
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return DRM_FORMAT_RGB888;
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case V4L2_PIX_FMT_RGB24:
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/* R G B <=> [24:0] B:G:R */
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return DRM_FORMAT_BGR888;
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case V4L2_PIX_FMT_BGR32:
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/* B G R A <=> [32:0] A:B:G:R */
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return DRM_FORMAT_XRGB8888;
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case V4L2_PIX_FMT_RGB32:
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/* R G B A <=> [32:0] A:B:G:R */
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return DRM_FORMAT_XBGR8888;
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case V4L2_PIX_FMT_UYVY:
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return DRM_FORMAT_UYVY;
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case V4L2_PIX_FMT_YUYV:
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return DRM_FORMAT_YUYV;
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case V4L2_PIX_FMT_YUV420:
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return DRM_FORMAT_YUV420;
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case V4L2_PIX_FMT_YUV422P:
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return DRM_FORMAT_YUV422;
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case V4L2_PIX_FMT_YVU420:
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return DRM_FORMAT_YVU420;
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case V4L2_PIX_FMT_NV12:
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return DRM_FORMAT_NV12;
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case V4L2_PIX_FMT_NV16:
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return DRM_FORMAT_NV16;
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}
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return -EINVAL;
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}
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void ipu_cpmem_zero(struct ipuv3_channel *ch)
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{
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struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
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void __iomem *base = p;
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int i;
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for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
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writel(0, base + i * sizeof(u32));
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
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void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
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void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
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{
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struct ipu_soc *ipu = ch->ipu;
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u32 val;
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if (ipu->ipu_type == IPUV3EX)
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ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
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val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
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val |= 1 << (ch->num % 32);
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ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
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};
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
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void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
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{
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if (bufnum)
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ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
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else
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ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
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void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8);
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ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1);
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};
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EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
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void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
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{
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id &= 0x3;
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ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
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void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
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};
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
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void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
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void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
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enum ipu_rotate_mode rot)
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{
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u32 temp_rot = bitrev8(rot) >> 5;
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ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);
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int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
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const struct ipu_rgb *rgb)
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{
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int bpp = 0, npb = 0, ro, go, bo, to;
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ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
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go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
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bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
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to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
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ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
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ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
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ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
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if (rgb->transp.length) {
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ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
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rgb->transp.length - 1);
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ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
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} else {
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ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
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ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
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rgb->bits_per_pixel);
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}
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switch (rgb->bits_per_pixel) {
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case 32:
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bpp = 0;
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npb = 15;
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break;
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case 24:
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bpp = 1;
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npb = 19;
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break;
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case 16:
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bpp = 3;
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npb = 31;
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break;
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case 8:
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bpp = 5;
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npb = 63;
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break;
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default:
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return -EINVAL;
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}
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ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
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ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
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ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
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int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
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{
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int bpp = 0, npb = 0;
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switch (width) {
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case 32:
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bpp = 0;
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npb = 15;
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break;
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case 24:
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bpp = 1;
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npb = 19;
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break;
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case 16:
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bpp = 3;
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npb = 31;
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break;
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case 8:
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bpp = 5;
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npb = 63;
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break;
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default:
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return -EINVAL;
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}
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ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
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ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
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ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
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void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
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{
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switch (pixel_format) {
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case V4L2_PIX_FMT_UYVY:
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ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
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ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
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ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
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break;
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case V4L2_PIX_FMT_YUYV:
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ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
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ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
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ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
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break;
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}
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
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void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
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u32 pixel_format, int stride,
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int u_offset, int v_offset)
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{
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switch (pixel_format) {
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case V4L2_PIX_FMT_YUV420:
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case V4L2_PIX_FMT_YUV422P:
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ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
|
|
break;
|
|
case V4L2_PIX_FMT_YVU420:
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
|
|
break;
|
|
case V4L2_PIX_FMT_NV12:
|
|
case V4L2_PIX_FMT_NV16:
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
|
|
break;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
|
|
|
|
void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
|
|
u32 pixel_format, int stride, int height)
|
|
{
|
|
int u_offset, v_offset;
|
|
int uv_stride = 0;
|
|
|
|
switch (pixel_format) {
|
|
case V4L2_PIX_FMT_YUV420:
|
|
case V4L2_PIX_FMT_YVU420:
|
|
uv_stride = stride / 2;
|
|
u_offset = stride * height;
|
|
v_offset = u_offset + (uv_stride * height / 2);
|
|
ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_YUV422P:
|
|
uv_stride = stride / 2;
|
|
u_offset = stride * height;
|
|
v_offset = u_offset + (uv_stride * height);
|
|
ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_NV12:
|
|
case V4L2_PIX_FMT_NV16:
|
|
u_offset = stride * height;
|
|
ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
|
|
u_offset, 0);
|
|
break;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
|
|
|
|
static const struct ipu_rgb def_rgb_32 = {
|
|
.red = { .offset = 16, .length = 8, },
|
|
.green = { .offset = 8, .length = 8, },
|
|
.blue = { .offset = 0, .length = 8, },
|
|
.transp = { .offset = 24, .length = 8, },
|
|
.bits_per_pixel = 32,
|
|
};
|
|
|
|
static const struct ipu_rgb def_bgr_32 = {
|
|
.red = { .offset = 0, .length = 8, },
|
|
.green = { .offset = 8, .length = 8, },
|
|
.blue = { .offset = 16, .length = 8, },
|
|
.transp = { .offset = 24, .length = 8, },
|
|
.bits_per_pixel = 32,
|
|
};
|
|
|
|
static const struct ipu_rgb def_rgb_24 = {
|
|
.red = { .offset = 16, .length = 8, },
|
|
.green = { .offset = 8, .length = 8, },
|
|
.blue = { .offset = 0, .length = 8, },
|
|
.transp = { .offset = 0, .length = 0, },
|
|
.bits_per_pixel = 24,
|
|
};
|
|
|
|
static const struct ipu_rgb def_bgr_24 = {
|
|
.red = { .offset = 0, .length = 8, },
|
|
.green = { .offset = 8, .length = 8, },
|
|
.blue = { .offset = 16, .length = 8, },
|
|
.transp = { .offset = 0, .length = 0, },
|
|
.bits_per_pixel = 24,
|
|
};
|
|
|
|
static const struct ipu_rgb def_rgb_16 = {
|
|
.red = { .offset = 11, .length = 5, },
|
|
.green = { .offset = 5, .length = 6, },
|
|
.blue = { .offset = 0, .length = 5, },
|
|
.transp = { .offset = 0, .length = 0, },
|
|
.bits_per_pixel = 16,
|
|
};
|
|
|
|
static const struct ipu_rgb def_bgr_16 = {
|
|
.red = { .offset = 0, .length = 5, },
|
|
.green = { .offset = 5, .length = 6, },
|
|
.blue = { .offset = 11, .length = 5, },
|
|
.transp = { .offset = 0, .length = 0, },
|
|
.bits_per_pixel = 16,
|
|
};
|
|
|
|
#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
|
|
#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * (y) / 4) + (x) / 2)
|
|
#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * pix->height / 4) + \
|
|
(pix->width * (y) / 4) + (x) / 2)
|
|
#define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * (y) / 2) + (x) / 2)
|
|
#define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * pix->height / 2) + \
|
|
(pix->width * (y) / 2) + (x) / 2)
|
|
#define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * (y) / 2) + (x))
|
|
#define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \
|
|
(pix->width * y) + (x))
|
|
|
|
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
|
|
{
|
|
switch (drm_fourcc) {
|
|
case DRM_FORMAT_YUV420:
|
|
case DRM_FORMAT_YVU420:
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_YUV422:
|
|
case DRM_FORMAT_YVU422:
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_NV12:
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_NV16:
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_UYVY:
|
|
/* bits/pixel */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_YUYV:
|
|
/* bits/pixel */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
|
|
/* pix format */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
|
|
/* burst size */
|
|
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
|
|
break;
|
|
case DRM_FORMAT_ABGR8888:
|
|
case DRM_FORMAT_XBGR8888:
|
|
ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
|
|
break;
|
|
case DRM_FORMAT_ARGB8888:
|
|
case DRM_FORMAT_XRGB8888:
|
|
ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
|
|
break;
|
|
case DRM_FORMAT_BGR888:
|
|
ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
|
|
break;
|
|
case DRM_FORMAT_RGB888:
|
|
ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
|
|
break;
|
|
case DRM_FORMAT_RGB565:
|
|
ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
|
|
break;
|
|
case DRM_FORMAT_BGR565:
|
|
ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
|
|
|
|
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
|
|
{
|
|
struct v4l2_pix_format *pix = &image->pix;
|
|
int offset, u_offset, v_offset;
|
|
|
|
pr_debug("%s: resolution: %dx%d stride: %d\n",
|
|
__func__, pix->width, pix->height,
|
|
pix->bytesperline);
|
|
|
|
ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
|
|
ipu_cpmem_set_stride(ch, pix->bytesperline);
|
|
|
|
ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
|
|
|
|
switch (pix->pixelformat) {
|
|
case V4L2_PIX_FMT_YUV420:
|
|
case V4L2_PIX_FMT_YVU420:
|
|
offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
|
|
u_offset = U_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
v_offset = V_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
|
|
ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
|
|
pix->bytesperline,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_YUV422P:
|
|
offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
|
|
u_offset = U2_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
v_offset = V2_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
|
|
ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
|
|
pix->bytesperline,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_NV12:
|
|
offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
|
|
u_offset = UV_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
v_offset = 0;
|
|
|
|
ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
|
|
pix->bytesperline,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_NV16:
|
|
offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
|
|
u_offset = UV2_OFFSET(pix, image->rect.left,
|
|
image->rect.top) - offset;
|
|
v_offset = 0;
|
|
|
|
ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
|
|
pix->bytesperline,
|
|
u_offset, v_offset);
|
|
break;
|
|
case V4L2_PIX_FMT_UYVY:
|
|
case V4L2_PIX_FMT_YUYV:
|
|
case V4L2_PIX_FMT_RGB565:
|
|
offset = image->rect.left * 2 +
|
|
image->rect.top * pix->bytesperline;
|
|
break;
|
|
case V4L2_PIX_FMT_RGB32:
|
|
case V4L2_PIX_FMT_BGR32:
|
|
offset = image->rect.left * 4 +
|
|
image->rect.top * pix->bytesperline;
|
|
break;
|
|
case V4L2_PIX_FMT_RGB24:
|
|
case V4L2_PIX_FMT_BGR24:
|
|
offset = image->rect.left * 3 +
|
|
image->rect.top * pix->bytesperline;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
|
|
ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
|
|
|
|
void ipu_cpmem_dump(struct ipuv3_channel *ch)
|
|
{
|
|
struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
|
|
struct ipu_soc *ipu = ch->ipu;
|
|
int chno = ch->num;
|
|
|
|
dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno,
|
|
readl(&p->word[0].data[0]),
|
|
readl(&p->word[0].data[1]),
|
|
readl(&p->word[0].data[2]),
|
|
readl(&p->word[0].data[3]),
|
|
readl(&p->word[0].data[4]));
|
|
dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno,
|
|
readl(&p->word[1].data[0]),
|
|
readl(&p->word[1].data[1]),
|
|
readl(&p->word[1].data[2]),
|
|
readl(&p->word[1].data[3]),
|
|
readl(&p->word[1].data[4]));
|
|
dev_dbg(ipu->dev, "PFS 0x%x, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_PFS));
|
|
dev_dbg(ipu->dev, "BPP 0x%x, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_BPP));
|
|
dev_dbg(ipu->dev, "NPB 0x%x\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_NPB));
|
|
|
|
dev_dbg(ipu->dev, "FW %d, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_FW));
|
|
dev_dbg(ipu->dev, "FH %d, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_FH));
|
|
dev_dbg(ipu->dev, "EBA0 0x%x\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3);
|
|
dev_dbg(ipu->dev, "EBA1 0x%x\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3);
|
|
dev_dbg(ipu->dev, "Stride %d\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_SL));
|
|
dev_dbg(ipu->dev, "scan_order %d\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_SO));
|
|
dev_dbg(ipu->dev, "uv_stride %d\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_SLUV));
|
|
dev_dbg(ipu->dev, "u_offset 0x%x\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3);
|
|
dev_dbg(ipu->dev, "v_offset 0x%x\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3);
|
|
|
|
dev_dbg(ipu->dev, "Width0 %d+1, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_WID0));
|
|
dev_dbg(ipu->dev, "Width1 %d+1, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_WID1));
|
|
dev_dbg(ipu->dev, "Width2 %d+1, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_WID2));
|
|
dev_dbg(ipu->dev, "Width3 %d+1, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_WID3));
|
|
dev_dbg(ipu->dev, "Offset0 %d, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_OFS0));
|
|
dev_dbg(ipu->dev, "Offset1 %d, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_OFS1));
|
|
dev_dbg(ipu->dev, "Offset2 %d, ",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_OFS2));
|
|
dev_dbg(ipu->dev, "Offset3 %d\n",
|
|
ipu_ch_param_read_field(ch, IPU_FIELD_OFS3));
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_cpmem_dump);
|
|
|
|
int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
|
|
{
|
|
struct ipu_cpmem *cpmem;
|
|
|
|
cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
|
|
if (!cpmem)
|
|
return -ENOMEM;
|
|
|
|
ipu->cpmem_priv = cpmem;
|
|
|
|
spin_lock_init(&cpmem->lock);
|
|
cpmem->base = devm_ioremap(dev, base, SZ_128K);
|
|
if (!cpmem->base)
|
|
return -ENOMEM;
|
|
|
|
dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
|
|
base, cpmem->base);
|
|
cpmem->ipu = ipu;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ipu_cpmem_exit(struct ipu_soc *ipu)
|
|
{
|
|
}
|