769 lines
20 KiB
C
769 lines
20 KiB
C
/*
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* Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
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*
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* Copyright (C) 2010 Samsung Electronics Co., Ltd
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* Author: Sylwester Nawrocki, s.nawrocki@samsung.com
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*
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* Based on original driver authored by Dongsoo Nathaniel Kim
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* and HeungJun Kim <riverful.kim@samsung.com>.
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*
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* Based on mt9v011 Micron Digital Image Sensor driver
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* Copyright (c) 2009 Mauro Carvalho Chehab
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/i2c.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-mediabus.h>
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#include <media/v4l2-ctrls.h>
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#include <media/sr030pc30.h>
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static int debug;
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module_param(debug, int, 0644);
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#define MODULE_NAME "SR030PC30"
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/*
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* Register offsets within a page
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* b15..b8 - page id, b7..b0 - register address
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*/
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#define POWER_CTRL_REG 0x0001
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#define PAGEMODE_REG 0x03
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#define DEVICE_ID_REG 0x0004
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#define NOON010PC30_ID 0x86
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#define SR030PC30_ID 0x8C
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#define VDO_CTL1_REG 0x0010
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#define SUBSAMPL_NONE_VGA 0
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#define SUBSAMPL_QVGA 0x10
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#define SUBSAMPL_QQVGA 0x20
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#define VDO_CTL2_REG 0x0011
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#define SYNC_CTL_REG 0x0012
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#define WIN_ROWH_REG 0x0020
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#define WIN_ROWL_REG 0x0021
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#define WIN_COLH_REG 0x0022
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#define WIN_COLL_REG 0x0023
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#define WIN_HEIGHTH_REG 0x0024
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#define WIN_HEIGHTL_REG 0x0025
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#define WIN_WIDTHH_REG 0x0026
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#define WIN_WIDTHL_REG 0x0027
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#define HBLANKH_REG 0x0040
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#define HBLANKL_REG 0x0041
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#define VSYNCH_REG 0x0042
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#define VSYNCL_REG 0x0043
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/* page 10 */
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#define ISP_CTL_REG(n) (0x1010 + (n))
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#define YOFS_REG 0x1040
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#define DARK_YOFS_REG 0x1041
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#define AG_ABRTH_REG 0x1050
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#define SAT_CTL_REG 0x1060
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#define BSAT_REG 0x1061
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#define RSAT_REG 0x1062
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#define AG_SAT_TH_REG 0x1063
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/* page 11 */
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#define ZLPF_CTRL_REG 0x1110
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#define ZLPF_CTRL2_REG 0x1112
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#define ZLPF_AGH_THR_REG 0x1121
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#define ZLPF_THR_REG 0x1160
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#define ZLPF_DYN_THR_REG 0x1160
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/* page 12 */
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#define YCLPF_CTL1_REG 0x1240
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#define YCLPF_CTL2_REG 0x1241
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#define YCLPF_THR_REG 0x1250
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#define BLPF_CTL_REG 0x1270
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#define BLPF_THR1_REG 0x1274
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#define BLPF_THR2_REG 0x1275
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/* page 14 - Lens Shading Compensation */
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#define LENS_CTRL_REG 0x1410
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#define LENS_XCEN_REG 0x1420
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#define LENS_YCEN_REG 0x1421
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#define LENS_R_COMP_REG 0x1422
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#define LENS_G_COMP_REG 0x1423
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#define LENS_B_COMP_REG 0x1424
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/* page 15 - Color correction */
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#define CMC_CTL_REG 0x1510
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#define CMC_OFSGH_REG 0x1514
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#define CMC_OFSGL_REG 0x1516
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#define CMC_SIGN_REG 0x1517
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/* Color correction coefficients */
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#define CMC_COEF_REG(n) (0x1530 + (n))
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/* Color correction offset coefficients */
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#define CMC_OFS_REG(n) (0x1540 + (n))
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/* page 16 - Gamma correction */
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#define GMA_CTL_REG 0x1610
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/* Gamma correction coefficients 0.14 */
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#define GMA_COEF_REG(n) (0x1630 + (n))
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/* page 20 - Auto Exposure */
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#define AE_CTL1_REG 0x2010
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#define AE_CTL2_REG 0x2011
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#define AE_FRM_CTL_REG 0x2020
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#define AE_FINE_CTL_REG(n) (0x2028 + (n))
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#define EXP_TIMEH_REG 0x2083
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#define EXP_TIMEM_REG 0x2084
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#define EXP_TIMEL_REG 0x2085
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#define EXP_MMINH_REG 0x2086
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#define EXP_MMINL_REG 0x2087
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#define EXP_MMAXH_REG 0x2088
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#define EXP_MMAXM_REG 0x2089
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#define EXP_MMAXL_REG 0x208A
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/* page 22 - Auto White Balance */
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#define AWB_CTL1_REG 0x2210
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#define AWB_ENABLE 0x80
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#define AWB_CTL2_REG 0x2211
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#define MWB_ENABLE 0x01
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/* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
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#define AWB_RGAIN_REG 0x2280
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#define AWB_GGAIN_REG 0x2281
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#define AWB_BGAIN_REG 0x2282
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#define AWB_RMAX_REG 0x2283
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#define AWB_RMIN_REG 0x2284
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#define AWB_BMAX_REG 0x2285
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#define AWB_BMIN_REG 0x2286
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/* R, B gain range in bright light conditions */
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#define AWB_RMAXB_REG 0x2287
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#define AWB_RMINB_REG 0x2288
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#define AWB_BMAXB_REG 0x2289
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#define AWB_BMINB_REG 0x228A
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/* manual white balance, when AWB_CTL2[0]=1 */
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#define MWB_RGAIN_REG 0x22B2
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#define MWB_BGAIN_REG 0x22B3
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/* the token to mark an array end */
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#define REG_TERM 0xFFFF
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/* Minimum and maximum exposure time in ms */
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#define EXPOS_MIN_MS 1
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#define EXPOS_MAX_MS 125
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struct sr030pc30_info {
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struct v4l2_subdev sd;
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struct v4l2_ctrl_handler hdl;
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const struct sr030pc30_platform_data *pdata;
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const struct sr030pc30_format *curr_fmt;
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const struct sr030pc30_frmsize *curr_win;
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unsigned int hflip:1;
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unsigned int vflip:1;
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unsigned int sleep:1;
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struct {
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/* auto whitebalance control cluster */
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struct v4l2_ctrl *awb;
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struct v4l2_ctrl *red;
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struct v4l2_ctrl *blue;
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};
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struct {
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/* auto exposure control cluster */
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struct v4l2_ctrl *autoexp;
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struct v4l2_ctrl *exp;
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};
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u8 i2c_reg_page;
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};
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struct sr030pc30_format {
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enum v4l2_mbus_pixelcode code;
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enum v4l2_colorspace colorspace;
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u16 ispctl1_reg;
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};
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struct sr030pc30_frmsize {
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u16 width;
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u16 height;
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int vid_ctl1;
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};
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struct i2c_regval {
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u16 addr;
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u16 val;
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};
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/* supported resolutions */
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static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
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{
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.width = 640,
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.height = 480,
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.vid_ctl1 = SUBSAMPL_NONE_VGA,
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}, {
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.width = 320,
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.height = 240,
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.vid_ctl1 = SUBSAMPL_QVGA,
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}, {
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.width = 160,
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.height = 120,
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.vid_ctl1 = SUBSAMPL_QQVGA,
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},
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};
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/* supported pixel formats */
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static const struct sr030pc30_format sr030pc30_formats[] = {
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{
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.code = V4L2_MBUS_FMT_YUYV8_2X8,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.ispctl1_reg = 0x03,
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}, {
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.code = V4L2_MBUS_FMT_YVYU8_2X8,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.ispctl1_reg = 0x02,
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}, {
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.code = V4L2_MBUS_FMT_VYUY8_2X8,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.ispctl1_reg = 0,
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}, {
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.code = V4L2_MBUS_FMT_UYVY8_2X8,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.ispctl1_reg = 0x01,
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}, {
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.code = V4L2_MBUS_FMT_RGB565_2X8_BE,
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.colorspace = V4L2_COLORSPACE_JPEG,
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.ispctl1_reg = 0x40,
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},
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};
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static const struct i2c_regval sr030pc30_base_regs[] = {
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/* Window size and position within pixel matrix */
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{ WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
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{ WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
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{ WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
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{ WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
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{ HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
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{ VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
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{ SYNC_CTL_REG, 0 },
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/* Color corection and saturation */
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{ ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
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{ DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
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{ SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
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{ AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
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{ CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
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{ CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
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{ CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
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{ CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
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{ CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
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{ CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
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{ CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
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{ CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
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{ CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
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{ CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
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{ CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
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/* Color corection coefficients */
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{ GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
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{ GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
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{ GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
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{ GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
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{ GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
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{ GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
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{ GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
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{ GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
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/* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
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{ ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
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{ ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
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{ ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
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{ YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
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{ BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
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{ BLPF_THR2_REG, 0x04 },
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/* Automatic white balance */
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{ AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
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{ AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
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{ AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
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{ AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
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{ AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
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/* Auto exposure */
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{ AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
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{ AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
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{ AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
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/* Lens shading compensation */
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{ LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
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{ LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
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{ LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
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{ REG_TERM, 0 },
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};
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static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
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{
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return container_of(sd, struct sr030pc30_info, sd);
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}
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static inline int set_i2c_page(struct sr030pc30_info *info,
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struct i2c_client *client, unsigned int reg)
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{
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int ret = 0;
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u32 page = reg >> 8 & 0xFF;
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if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
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ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
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if (!ret)
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info->i2c_reg_page = page;
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}
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return ret;
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}
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static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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struct sr030pc30_info *info = to_sr030pc30(sd);
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int ret = set_i2c_page(info, client, reg_addr);
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if (!ret)
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ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
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return ret;
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}
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static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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struct sr030pc30_info *info = to_sr030pc30(sd);
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int ret = set_i2c_page(info, client, reg_addr);
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if (!ret)
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ret = i2c_smbus_write_byte_data(
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client, reg_addr & 0xFF, val);
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return ret;
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}
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static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
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const struct i2c_regval *msg)
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{
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while (msg->addr != REG_TERM) {
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int ret = cam_i2c_write(sd, msg->addr, msg->val);
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if (ret)
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return ret;
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msg++;
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}
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return 0;
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}
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/* Device reset and sleep mode control */
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static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
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bool reset, bool sleep)
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{
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struct sr030pc30_info *info = to_sr030pc30(sd);
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u8 reg = sleep ? 0xF1 : 0xF0;
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int ret = 0;
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if (reset)
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ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
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if (!ret) {
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ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
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if (!ret) {
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info->sleep = sleep;
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if (reset)
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info->i2c_reg_page = -1;
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}
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}
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return ret;
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}
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static int sr030pc30_set_flip(struct v4l2_subdev *sd)
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{
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struct sr030pc30_info *info = to_sr030pc30(sd);
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s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
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if (reg < 0)
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return reg;
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reg &= 0x7C;
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if (info->hflip)
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reg |= 0x01;
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if (info->vflip)
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reg |= 0x02;
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return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
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}
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/* Configure resolution, color format and image flip */
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static int sr030pc30_set_params(struct v4l2_subdev *sd)
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{
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struct sr030pc30_info *info = to_sr030pc30(sd);
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int ret;
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if (!info->curr_win)
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return -EINVAL;
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/* Configure the resolution through subsampling */
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ret = cam_i2c_write(sd, VDO_CTL1_REG,
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info->curr_win->vid_ctl1);
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if (!ret && info->curr_fmt)
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ret = cam_i2c_write(sd, ISP_CTL_REG(0),
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info->curr_fmt->ispctl1_reg);
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if (!ret)
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ret = sr030pc30_set_flip(sd);
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return ret;
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}
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/* Find nearest matching image pixel size. */
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static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
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{
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unsigned int min_err = ~0;
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int i = ARRAY_SIZE(sr030pc30_sizes);
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const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
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*match = NULL;
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while (i--) {
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int err = abs(fsize->width - mf->width)
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+ abs(fsize->height - mf->height);
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if (err < min_err) {
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min_err = err;
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match = fsize;
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}
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fsize++;
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}
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if (match) {
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mf->width = match->width;
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mf->height = match->height;
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return 0;
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}
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return -EINVAL;
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}
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static int sr030pc30_s_ctrl(struct v4l2_ctrl *ctrl)
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{
|
|
struct sr030pc30_info *info =
|
|
container_of(ctrl->handler, struct sr030pc30_info, hdl);
|
|
struct v4l2_subdev *sd = &info->sd;
|
|
int ret = 0;
|
|
|
|
v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
|
|
__func__, ctrl->id, ctrl->val);
|
|
|
|
switch (ctrl->id) {
|
|
case V4L2_CID_AUTO_WHITE_BALANCE:
|
|
if (ctrl->is_new) {
|
|
ret = cam_i2c_write(sd, AWB_CTL2_REG,
|
|
ctrl->val ? 0x2E : 0x2F);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, AWB_CTL1_REG,
|
|
ctrl->val ? 0xFB : 0x7B);
|
|
}
|
|
if (!ret && info->blue->is_new)
|
|
ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val);
|
|
if (!ret && info->red->is_new)
|
|
ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val);
|
|
return ret;
|
|
|
|
case V4L2_CID_EXPOSURE_AUTO:
|
|
/* auto anti-flicker is also enabled here */
|
|
if (ctrl->is_new)
|
|
ret = cam_i2c_write(sd, AE_CTL1_REG,
|
|
ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C);
|
|
if (info->exp->is_new) {
|
|
unsigned long expos = info->exp->val;
|
|
|
|
expos = expos * info->pdata->clk_rate / (8 * 1000);
|
|
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_TIMEH_REG,
|
|
expos >> 16 & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_TIMEM_REG,
|
|
expos >> 8 & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_TIMEL_REG,
|
|
expos & 0xFF);
|
|
}
|
|
return ret;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sr030pc30_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
|
|
enum v4l2_mbus_pixelcode *code)
|
|
{
|
|
if (!code || index >= ARRAY_SIZE(sr030pc30_formats))
|
|
return -EINVAL;
|
|
|
|
*code = sr030pc30_formats[index].code;
|
|
return 0;
|
|
}
|
|
|
|
static int sr030pc30_g_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
struct sr030pc30_info *info = to_sr030pc30(sd);
|
|
int ret;
|
|
|
|
if (!mf)
|
|
return -EINVAL;
|
|
|
|
if (!info->curr_win || !info->curr_fmt) {
|
|
ret = sr030pc30_set_params(sd);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
mf->width = info->curr_win->width;
|
|
mf->height = info->curr_win->height;
|
|
mf->code = info->curr_fmt->code;
|
|
mf->colorspace = info->curr_fmt->colorspace;
|
|
mf->field = V4L2_FIELD_NONE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Return nearest media bus frame format. */
|
|
static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
int i = ARRAY_SIZE(sr030pc30_formats);
|
|
|
|
sr030pc30_try_frame_size(mf);
|
|
|
|
while (i--)
|
|
if (mf->code == sr030pc30_formats[i].code)
|
|
break;
|
|
|
|
mf->code = sr030pc30_formats[i].code;
|
|
|
|
return &sr030pc30_formats[i];
|
|
}
|
|
|
|
/* Return nearest media bus frame format. */
|
|
static int sr030pc30_try_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
if (!sd || !mf)
|
|
return -EINVAL;
|
|
|
|
try_fmt(sd, mf);
|
|
return 0;
|
|
}
|
|
|
|
static int sr030pc30_s_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_mbus_framefmt *mf)
|
|
{
|
|
struct sr030pc30_info *info = to_sr030pc30(sd);
|
|
|
|
if (!sd || !mf)
|
|
return -EINVAL;
|
|
|
|
info->curr_fmt = try_fmt(sd, mf);
|
|
|
|
return sr030pc30_set_params(sd);
|
|
}
|
|
|
|
static int sr030pc30_base_config(struct v4l2_subdev *sd)
|
|
{
|
|
struct sr030pc30_info *info = to_sr030pc30(sd);
|
|
int ret;
|
|
unsigned long expmin, expmax;
|
|
|
|
ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
|
|
if (!ret) {
|
|
info->curr_fmt = &sr030pc30_formats[0];
|
|
info->curr_win = &sr030pc30_sizes[0];
|
|
ret = sr030pc30_set_params(sd);
|
|
}
|
|
if (!ret)
|
|
ret = sr030pc30_pwr_ctrl(sd, false, false);
|
|
|
|
if (!ret && !info->pdata)
|
|
return ret;
|
|
|
|
expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
|
|
expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
|
|
|
|
v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
|
|
expmin, expmax);
|
|
|
|
/* Setting up manual exposure time range */
|
|
ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
|
|
if (!ret)
|
|
ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
|
|
{
|
|
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
|
struct sr030pc30_info *info = to_sr030pc30(sd);
|
|
const struct sr030pc30_platform_data *pdata = info->pdata;
|
|
int ret;
|
|
|
|
if (pdata == NULL) {
|
|
WARN(1, "No platform data!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Put sensor into power sleep mode before switching off
|
|
* power and disabling MCLK.
|
|
*/
|
|
if (!on)
|
|
sr030pc30_pwr_ctrl(sd, false, true);
|
|
|
|
/* set_power controls sensor's power and clock */
|
|
if (pdata->set_power) {
|
|
ret = pdata->set_power(&client->dev, on);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (on) {
|
|
ret = sr030pc30_base_config(sd);
|
|
} else {
|
|
ret = 0;
|
|
info->curr_win = NULL;
|
|
info->curr_fmt = NULL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct v4l2_ctrl_ops sr030pc30_ctrl_ops = {
|
|
.s_ctrl = sr030pc30_s_ctrl,
|
|
};
|
|
|
|
static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
|
|
.s_power = sr030pc30_s_power,
|
|
.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
|
|
.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
|
|
.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
|
|
.g_ctrl = v4l2_subdev_g_ctrl,
|
|
.s_ctrl = v4l2_subdev_s_ctrl,
|
|
.queryctrl = v4l2_subdev_queryctrl,
|
|
.querymenu = v4l2_subdev_querymenu,
|
|
};
|
|
|
|
static const struct v4l2_subdev_video_ops sr030pc30_video_ops = {
|
|
.g_mbus_fmt = sr030pc30_g_fmt,
|
|
.s_mbus_fmt = sr030pc30_s_fmt,
|
|
.try_mbus_fmt = sr030pc30_try_fmt,
|
|
.enum_mbus_fmt = sr030pc30_enum_fmt,
|
|
};
|
|
|
|
static const struct v4l2_subdev_ops sr030pc30_ops = {
|
|
.core = &sr030pc30_core_ops,
|
|
.video = &sr030pc30_video_ops,
|
|
};
|
|
|
|
/*
|
|
* Detect sensor type. Return 0 if SR030PC30 was detected
|
|
* or -ENODEV otherwise.
|
|
*/
|
|
static int sr030pc30_detect(struct i2c_client *client)
|
|
{
|
|
const struct sr030pc30_platform_data *pdata
|
|
= client->dev.platform_data;
|
|
int ret;
|
|
|
|
/* Enable sensor's power and clock */
|
|
if (pdata->set_power) {
|
|
ret = pdata->set_power(&client->dev, 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
|
|
|
|
if (pdata->set_power)
|
|
pdata->set_power(&client->dev, 0);
|
|
|
|
if (ret < 0) {
|
|
dev_err(&client->dev, "%s: I2C read failed\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
return ret == SR030PC30_ID ? 0 : -ENODEV;
|
|
}
|
|
|
|
|
|
static int sr030pc30_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct sr030pc30_info *info;
|
|
struct v4l2_subdev *sd;
|
|
struct v4l2_ctrl_handler *hdl;
|
|
const struct sr030pc30_platform_data *pdata
|
|
= client->dev.platform_data;
|
|
int ret;
|
|
|
|
if (!pdata) {
|
|
dev_err(&client->dev, "No platform data!");
|
|
return -EIO;
|
|
}
|
|
|
|
ret = sr030pc30_detect(client);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
sd = &info->sd;
|
|
strcpy(sd->name, MODULE_NAME);
|
|
info->pdata = client->dev.platform_data;
|
|
|
|
v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
|
|
|
|
hdl = &info->hdl;
|
|
v4l2_ctrl_handler_init(hdl, 6);
|
|
info->awb = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
|
|
V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
|
|
info->red = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
|
|
V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
|
|
info->blue = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
|
|
V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
|
|
info->autoexp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
|
|
V4L2_CID_EXPOSURE_AUTO, 0, 1, 1, 1);
|
|
info->exp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
|
|
V4L2_CID_EXPOSURE, EXPOS_MIN_MS, EXPOS_MAX_MS, 1, 30);
|
|
sd->ctrl_handler = hdl;
|
|
if (hdl->error) {
|
|
int err = hdl->error;
|
|
|
|
v4l2_ctrl_handler_free(hdl);
|
|
return err;
|
|
}
|
|
v4l2_ctrl_auto_cluster(3, &info->awb, 0, false);
|
|
v4l2_ctrl_auto_cluster(2, &info->autoexp, V4L2_EXPOSURE_MANUAL, false);
|
|
v4l2_ctrl_handler_setup(hdl);
|
|
|
|
info->i2c_reg_page = -1;
|
|
info->hflip = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sr030pc30_remove(struct i2c_client *client)
|
|
{
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
|
|
v4l2_device_unregister_subdev(sd);
|
|
v4l2_ctrl_handler_free(sd->ctrl_handler);
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id sr030pc30_id[] = {
|
|
{ MODULE_NAME, 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
|
|
|
|
|
|
static struct i2c_driver sr030pc30_i2c_driver = {
|
|
.driver = {
|
|
.name = MODULE_NAME
|
|
},
|
|
.probe = sr030pc30_probe,
|
|
.remove = sr030pc30_remove,
|
|
.id_table = sr030pc30_id,
|
|
};
|
|
|
|
module_i2c_driver(sr030pc30_i2c_driver);
|
|
|
|
MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
|
|
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
|
|
MODULE_LICENSE("GPL");
|