511 lines
14 KiB
C
511 lines
14 KiB
C
/*
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* isphist.c
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*
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* TI OMAP3 ISP - Histogram module
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*
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* Copyright (C) 2010 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Contacts: David Cohen <dacohen@gmail.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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* Sakari Ailus <sakari.ailus@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/device.h>
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#include "isp.h"
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#include "ispreg.h"
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#include "isphist.h"
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#define OMAP24XX_DMA_NO_DEVICE 0
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#define HIST_CONFIG_DMA 1
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#define HIST_USING_DMA(hist) ((hist)->dma_ch >= 0)
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/*
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* hist_reset_mem - clear Histogram memory before start stats engine.
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*/
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static void hist_reset_mem(struct ispstat *hist)
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{
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struct isp_device *isp = hist->isp;
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struct omap3isp_hist_config *conf = hist->priv;
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unsigned int i;
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isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
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/*
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* By setting it, the histogram internal buffer is being cleared at the
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* same time it's being read. This bit must be cleared afterwards.
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*/
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isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
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/*
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* We'll clear 4 words at each iteration for optimization. It avoids
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* 3/4 of the jumps. We also know HIST_MEM_SIZE is divisible by 4.
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*/
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for (i = OMAP3ISP_HIST_MEM_SIZE / 4; i > 0; i--) {
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isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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}
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isp_reg_clr(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
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hist->wait_acc_frames = conf->num_acc_frames;
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}
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static void hist_dma_config(struct ispstat *hist)
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{
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struct isp_device *isp = hist->isp;
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hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32;
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hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT;
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hist->dma_config.frame_count = 1;
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hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT;
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hist->dma_config.src_start = isp->mmio_base_phys[OMAP3_ISP_IOMEM_HIST]
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+ ISPHIST_DATA;
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hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC;
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hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC;
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}
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/*
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* hist_setup_regs - Helper function to update Histogram registers.
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*/
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static void hist_setup_regs(struct ispstat *hist, void *priv)
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{
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struct isp_device *isp = hist->isp;
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struct omap3isp_hist_config *conf = priv;
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int c;
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u32 cnt;
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u32 wb_gain;
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u32 reg_hor[OMAP3ISP_HIST_MAX_REGIONS];
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u32 reg_ver[OMAP3ISP_HIST_MAX_REGIONS];
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if (!hist->update || hist->state == ISPSTAT_DISABLED ||
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hist->state == ISPSTAT_DISABLING)
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return;
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cnt = conf->cfa << ISPHIST_CNT_CFA_SHIFT;
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wb_gain = conf->wg[0] << ISPHIST_WB_GAIN_WG00_SHIFT;
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wb_gain |= conf->wg[1] << ISPHIST_WB_GAIN_WG01_SHIFT;
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wb_gain |= conf->wg[2] << ISPHIST_WB_GAIN_WG02_SHIFT;
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if (conf->cfa == OMAP3ISP_HIST_CFA_BAYER)
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wb_gain |= conf->wg[3] << ISPHIST_WB_GAIN_WG03_SHIFT;
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/* Regions size and position */
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for (c = 0; c < OMAP3ISP_HIST_MAX_REGIONS; c++) {
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if (c < conf->num_regions) {
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reg_hor[c] = (conf->region[c].h_start <<
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ISPHIST_REG_START_SHIFT)
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| (conf->region[c].h_end <<
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ISPHIST_REG_END_SHIFT);
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reg_ver[c] = (conf->region[c].v_start <<
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ISPHIST_REG_START_SHIFT)
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| (conf->region[c].v_end <<
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ISPHIST_REG_END_SHIFT);
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} else {
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reg_hor[c] = 0;
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reg_ver[c] = 0;
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}
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}
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cnt |= conf->hist_bins << ISPHIST_CNT_BINS_SHIFT;
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switch (conf->hist_bins) {
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case OMAP3ISP_HIST_BINS_256:
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cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 8) <<
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ISPHIST_CNT_SHIFT_SHIFT;
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break;
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case OMAP3ISP_HIST_BINS_128:
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cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 7) <<
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ISPHIST_CNT_SHIFT_SHIFT;
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break;
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case OMAP3ISP_HIST_BINS_64:
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cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 6) <<
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ISPHIST_CNT_SHIFT_SHIFT;
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break;
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default: /* OMAP3ISP_HIST_BINS_32 */
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cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 5) <<
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ISPHIST_CNT_SHIFT_SHIFT;
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break;
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}
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hist_reset_mem(hist);
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isp_reg_writel(isp, cnt, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT);
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isp_reg_writel(isp, wb_gain, OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN);
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isp_reg_writel(isp, reg_hor[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ);
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isp_reg_writel(isp, reg_ver[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT);
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isp_reg_writel(isp, reg_hor[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ);
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isp_reg_writel(isp, reg_ver[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT);
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isp_reg_writel(isp, reg_hor[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ);
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isp_reg_writel(isp, reg_ver[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT);
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isp_reg_writel(isp, reg_hor[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ);
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isp_reg_writel(isp, reg_ver[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT);
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hist->update = 0;
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hist->config_counter += hist->inc_config;
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hist->inc_config = 0;
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hist->buf_size = conf->buf_size;
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}
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static void hist_enable(struct ispstat *hist, int enable)
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{
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if (enable) {
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isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
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ISPHIST_PCR_ENABLE);
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omap3isp_subclk_enable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
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} else {
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isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
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ISPHIST_PCR_ENABLE);
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omap3isp_subclk_disable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
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}
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}
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static int hist_busy(struct ispstat *hist)
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{
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return isp_reg_readl(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR)
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& ISPHIST_PCR_BUSY;
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}
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static void hist_dma_cb(int lch, u16 ch_status, void *data)
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{
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struct ispstat *hist = data;
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if (ch_status & ~OMAP_DMA_BLOCK_IRQ) {
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dev_dbg(hist->isp->dev, "hist: DMA error. status = 0x%04x\n",
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ch_status);
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omap_stop_dma(lch);
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hist_reset_mem(hist);
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atomic_set(&hist->buf_err, 1);
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}
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isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
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ISPHIST_CNT_CLEAR);
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omap3isp_stat_dma_isr(hist);
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if (hist->state != ISPSTAT_DISABLED)
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omap3isp_hist_dma_done(hist->isp);
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}
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static int hist_buf_dma(struct ispstat *hist)
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{
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dma_addr_t dma_addr = hist->active_buf->dma_addr;
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if (unlikely(!dma_addr)) {
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dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n");
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hist_reset_mem(hist);
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return STAT_NO_BUF;
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}
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isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
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isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
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ISPHIST_CNT_CLEAR);
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omap3isp_flush(hist->isp);
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hist->dma_config.dst_start = dma_addr;
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hist->dma_config.elem_count = hist->buf_size / sizeof(u32);
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omap_set_dma_params(hist->dma_ch, &hist->dma_config);
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omap_start_dma(hist->dma_ch);
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return STAT_BUF_WAITING_DMA;
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}
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static int hist_buf_pio(struct ispstat *hist)
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{
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struct isp_device *isp = hist->isp;
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u32 *buf = hist->active_buf->virt_addr;
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unsigned int i;
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if (!buf) {
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dev_dbg(isp->dev, "hist: invalid PIO buffer address\n");
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hist_reset_mem(hist);
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return STAT_NO_BUF;
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}
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isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
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/*
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* By setting it, the histogram internal buffer is being cleared at the
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* same time it's being read. This bit must be cleared just after all
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* data is acquired.
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*/
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isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
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/*
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* We'll read 4 times a 4-bytes-word at each iteration for
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* optimization. It avoids 3/4 of the jumps. We also know buf_size is
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* divisible by 16.
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*/
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for (i = hist->buf_size / 16; i > 0; i--) {
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*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
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}
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isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
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ISPHIST_CNT_CLEAR);
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return STAT_BUF_DONE;
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}
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/*
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* hist_buf_process - Callback from ISP driver for HIST interrupt.
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*/
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static int hist_buf_process(struct ispstat *hist)
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{
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struct omap3isp_hist_config *user_cfg = hist->priv;
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int ret;
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if (atomic_read(&hist->buf_err) || hist->state != ISPSTAT_ENABLED) {
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hist_reset_mem(hist);
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return STAT_NO_BUF;
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}
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if (--(hist->wait_acc_frames))
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return STAT_NO_BUF;
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if (HIST_USING_DMA(hist))
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ret = hist_buf_dma(hist);
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else
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ret = hist_buf_pio(hist);
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hist->wait_acc_frames = user_cfg->num_acc_frames;
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return ret;
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}
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static u32 hist_get_buf_size(struct omap3isp_hist_config *conf)
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{
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return OMAP3ISP_HIST_MEM_SIZE_BINS(conf->hist_bins) * conf->num_regions;
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}
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/*
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* hist_validate_params - Helper function to check user given params.
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* @new_conf: Pointer to user configuration structure.
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*
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* Returns 0 on success configuration.
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*/
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static int hist_validate_params(struct ispstat *hist, void *new_conf)
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{
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struct omap3isp_hist_config *user_cfg = new_conf;
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int c;
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u32 buf_size;
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if (user_cfg->cfa > OMAP3ISP_HIST_CFA_FOVEONX3)
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return -EINVAL;
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/* Regions size and position */
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if ((user_cfg->num_regions < OMAP3ISP_HIST_MIN_REGIONS) ||
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(user_cfg->num_regions > OMAP3ISP_HIST_MAX_REGIONS))
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return -EINVAL;
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/* Regions */
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for (c = 0; c < user_cfg->num_regions; c++) {
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if (user_cfg->region[c].h_start & ~ISPHIST_REG_START_END_MASK)
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return -EINVAL;
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if (user_cfg->region[c].h_end & ~ISPHIST_REG_START_END_MASK)
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return -EINVAL;
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if (user_cfg->region[c].v_start & ~ISPHIST_REG_START_END_MASK)
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return -EINVAL;
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if (user_cfg->region[c].v_end & ~ISPHIST_REG_START_END_MASK)
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return -EINVAL;
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if (user_cfg->region[c].h_start > user_cfg->region[c].h_end)
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return -EINVAL;
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if (user_cfg->region[c].v_start > user_cfg->region[c].v_end)
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return -EINVAL;
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}
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switch (user_cfg->num_regions) {
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case 1:
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if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_256)
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return -EINVAL;
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break;
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case 2:
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if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_128)
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return -EINVAL;
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break;
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default: /* 3 or 4 */
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if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_64)
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return -EINVAL;
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break;
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}
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buf_size = hist_get_buf_size(user_cfg);
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if (buf_size > user_cfg->buf_size)
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/* User's buf_size request wasn't enough */
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user_cfg->buf_size = buf_size;
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else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE)
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user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE;
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return 0;
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}
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static int hist_comp_params(struct ispstat *hist,
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struct omap3isp_hist_config *user_cfg)
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{
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struct omap3isp_hist_config *cur_cfg = hist->priv;
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int c;
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if (cur_cfg->cfa != user_cfg->cfa)
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return 1;
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if (cur_cfg->num_acc_frames != user_cfg->num_acc_frames)
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return 1;
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if (cur_cfg->hist_bins != user_cfg->hist_bins)
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return 1;
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for (c = 0; c < OMAP3ISP_HIST_MAX_WG; c++) {
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if (c == 3 && user_cfg->cfa == OMAP3ISP_HIST_CFA_FOVEONX3)
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break;
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else if (cur_cfg->wg[c] != user_cfg->wg[c])
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return 1;
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}
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if (cur_cfg->num_regions != user_cfg->num_regions)
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return 1;
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/* Regions */
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for (c = 0; c < user_cfg->num_regions; c++) {
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if (cur_cfg->region[c].h_start != user_cfg->region[c].h_start)
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return 1;
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if (cur_cfg->region[c].h_end != user_cfg->region[c].h_end)
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return 1;
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if (cur_cfg->region[c].v_start != user_cfg->region[c].v_start)
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return 1;
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if (cur_cfg->region[c].v_end != user_cfg->region[c].v_end)
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return 1;
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}
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return 0;
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}
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/*
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* hist_update_params - Helper function to check and store user given params.
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* @new_conf: Pointer to user configuration structure.
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*/
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static void hist_set_params(struct ispstat *hist, void *new_conf)
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{
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struct omap3isp_hist_config *user_cfg = new_conf;
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struct omap3isp_hist_config *cur_cfg = hist->priv;
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if (!hist->configured || hist_comp_params(hist, user_cfg)) {
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memcpy(cur_cfg, user_cfg, sizeof(*user_cfg));
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if (user_cfg->num_acc_frames == 0)
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user_cfg->num_acc_frames = 1;
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hist->inc_config++;
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hist->update = 1;
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/*
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* User might be asked for a bigger buffer than necessary for
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* this configuration. In order to return the right amount of
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* data during buffer request, let's calculate the size here
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* instead of stick with user_cfg->buf_size.
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*/
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cur_cfg->buf_size = hist_get_buf_size(cur_cfg);
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}
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}
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static long hist_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
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{
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struct ispstat *stat = v4l2_get_subdevdata(sd);
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switch (cmd) {
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case VIDIOC_OMAP3ISP_HIST_CFG:
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return omap3isp_stat_config(stat, arg);
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case VIDIOC_OMAP3ISP_STAT_REQ:
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return omap3isp_stat_request_statistics(stat, arg);
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case VIDIOC_OMAP3ISP_STAT_EN: {
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int *en = arg;
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return omap3isp_stat_enable(stat, !!*en);
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}
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}
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return -ENOIOCTLCMD;
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}
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static const struct ispstat_ops hist_ops = {
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.validate_params = hist_validate_params,
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.set_params = hist_set_params,
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.setup_regs = hist_setup_regs,
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.enable = hist_enable,
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.busy = hist_busy,
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.buf_process = hist_buf_process,
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};
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static const struct v4l2_subdev_core_ops hist_subdev_core_ops = {
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.ioctl = hist_ioctl,
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.subscribe_event = omap3isp_stat_subscribe_event,
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.unsubscribe_event = omap3isp_stat_unsubscribe_event,
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};
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static const struct v4l2_subdev_video_ops hist_subdev_video_ops = {
|
|
.s_stream = omap3isp_stat_s_stream,
|
|
};
|
|
|
|
static const struct v4l2_subdev_ops hist_subdev_ops = {
|
|
.core = &hist_subdev_core_ops,
|
|
.video = &hist_subdev_video_ops,
|
|
};
|
|
|
|
/*
|
|
* omap3isp_hist_init - Module Initialization.
|
|
*/
|
|
int omap3isp_hist_init(struct isp_device *isp)
|
|
{
|
|
struct ispstat *hist = &isp->isp_hist;
|
|
struct omap3isp_hist_config *hist_cfg;
|
|
int ret = -1;
|
|
|
|
hist_cfg = devm_kzalloc(isp->dev, sizeof(*hist_cfg), GFP_KERNEL);
|
|
if (hist_cfg == NULL)
|
|
return -ENOMEM;
|
|
|
|
hist->isp = isp;
|
|
|
|
if (HIST_CONFIG_DMA)
|
|
ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST",
|
|
hist_dma_cb, hist, &hist->dma_ch);
|
|
if (ret) {
|
|
if (HIST_CONFIG_DMA)
|
|
dev_warn(isp->dev, "hist: DMA request channel failed. "
|
|
"Using PIO only.\n");
|
|
hist->dma_ch = -1;
|
|
} else {
|
|
dev_dbg(isp->dev, "hist: DMA channel = %d\n", hist->dma_ch);
|
|
hist_dma_config(hist);
|
|
omap_enable_dma_irq(hist->dma_ch, OMAP_DMA_BLOCK_IRQ);
|
|
}
|
|
|
|
hist->ops = &hist_ops;
|
|
hist->priv = hist_cfg;
|
|
hist->event_type = V4L2_EVENT_OMAP3ISP_HIST;
|
|
|
|
ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops);
|
|
if (ret) {
|
|
if (HIST_USING_DMA(hist))
|
|
omap_free_dma(hist->dma_ch);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* omap3isp_hist_cleanup - Module cleanup.
|
|
*/
|
|
void omap3isp_hist_cleanup(struct isp_device *isp)
|
|
{
|
|
if (HIST_USING_DMA(&isp->isp_hist))
|
|
omap_free_dma(isp->isp_hist.dma_ch);
|
|
omap3isp_stat_cleanup(&isp->isp_hist);
|
|
}
|