712 lines
18 KiB
C
712 lines
18 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/power/qcom/apm.h>
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#include <soc/qcom/scm.h>
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/*
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* VDD_APCC
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* =============================================================
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* | VDD_MX | |
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* | ==========================|============= |
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* ___|___ ___|___ ___|___ ___|___ ___|___ ___|___
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* | | | | | | | | | | | |
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* | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC |
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* | HS | | | | | | HS | | | | HS |
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* |_______| |_______| |_______| |_______| |_______| |_______|
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* |_________| |_________| |__________|
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* | | |
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* ______|_____ ______|_____ _______|_____
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* | | | | | |
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* | | | | | |
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* | CPU MEM | | L2 MEM | | L3 MEM |
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* | Arrays | | Arrays | | Arrays |
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* | | | | | |
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* |____________| |____________| |_____________|
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*
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*/
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/* Register value definitions */
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#define APCS_GFMUXA_SEL_VAL 0x13
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#define APCS_GFMUXA_DESEL_VAL 0x03
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#define MSM_APM_MX_MODE_VAL 0x00
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#define MSM_APM_APCC_MODE_VAL 0x10
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#define MSM_APM_MX_DONE_VAL 0x00
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#define MSM_APM_APCC_DONE_VAL 0x03
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#define MSM_APM_OVERRIDE_SEL_VAL 0xb0
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#define MSM_APM_SEC_CLK_SEL_VAL 0x30
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#define SPM_EVENT_SET_VAL 0x01
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#define SPM_EVENT_CLEAR_VAL 0x00
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/* Register bit mask definitions */
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#define MSM_APM_CTL_STS_MASK 0x0f
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/* Register offset definitions */
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#define APCC_APM_MODE 0x00000098
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#define APCC_APM_CTL_STS 0x000000a8
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#define APCS_SPARE 0x00000068
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#define APCS_VERSION 0x00000fd0
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#define HMSS_VERSION_1P2 0x10020000
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#define MSM_APM_SWITCH_TIMEOUT_US 10
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#define SPM_WAKEUP_DELAY_US 2
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#define SPM_EVENT_NUM 6
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#define MSM_APM_DRIVER_NAME "qcom,msm-apm"
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asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
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enum {
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CLOCK_ASSERT_ENABLE,
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CLOCK_ASSERT_DISABLE,
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CLOCK_ASSERT_TOGGLE,
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};
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struct msm_apm_ctrl_dev {
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struct list_head list;
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struct device *dev;
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enum msm_apm_supply supply;
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spinlock_t lock;
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void __iomem *reg_base;
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void __iomem *apcs_csr_base;
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void __iomem **apcs_spm_events_addr;
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void __iomem *apc0_pll_ctl_addr;
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void __iomem *apc1_pll_ctl_addr;
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bool clk_src_override;
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u32 version;
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struct dentry *debugfs;
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};
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#if defined(CONFIG_DEBUG_FS)
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static struct dentry *apm_debugfs_base;
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#endif
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static DEFINE_MUTEX(apm_ctrl_list_mutex);
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static LIST_HEAD(apm_ctrl_list);
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/*
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* Get the resources associated with the APM controller from device tree
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* and remap all I/O addresses that are relevant to this HW revision.
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*/
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static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
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struct msm_apm_ctrl_dev *ctrl)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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static const char *res_name[SPM_EVENT_NUM] = {
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"apc0-l2-spm",
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"apc1-l2-spm",
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"apc0-cpu0-spm",
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"apc0-cpu1-spm",
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"apc1-cpu0-spm",
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"apc1-cpu1-spm"
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};
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int i, ret = 0;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
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if (!res) {
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dev_err(dev, "Missing PM APCC Global register physical address");
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return -EINVAL;
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}
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ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!ctrl->reg_base) {
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dev_err(dev, "Failed to map PM APCC Global registers\n");
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return -ENOMEM;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
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if (!res) {
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dev_err(dev, "Missing APCS CSR physical base address");
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return -EINVAL;
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}
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ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!ctrl->apcs_csr_base) {
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dev_err(dev, "Failed to map APCS CSR registers\n");
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return -ENOMEM;
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}
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ctrl->clk_src_override = of_property_read_bool(dev->of_node,
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"qcom,clock-source-override");
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if (ctrl->clk_src_override)
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dev_info(dev, "overriding clock sources across APM switch\n");
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ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
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if (ctrl->version >= HMSS_VERSION_1P2)
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return ret;
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ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
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SPM_EVENT_NUM
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* sizeof(void __iomem *),
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GFP_KERNEL);
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if (!ctrl->apcs_spm_events_addr) {
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dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
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return -ENOMEM;
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}
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for (i = 0; i < SPM_EVENT_NUM; i++) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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res_name[i]);
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if (!res) {
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dev_err(dev, "Missing address for %s\n", res_name[i]);
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ret = -EINVAL;
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goto free_events;
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}
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ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
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resource_size(res));
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if (!ctrl->apcs_spm_events_addr[i]) {
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dev_err(dev, "Failed to map %s\n", res_name[i]);
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ret = -ENOMEM;
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goto free_events;
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}
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dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
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&res->start, ctrl->apcs_spm_events_addr[i]);
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"apc0-pll-ctl");
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if (!res) {
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dev_err(dev, "Missing APC0 PLL CTL physical address\n");
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ret = -EINVAL;
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goto free_events;
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}
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ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
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res->start,
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resource_size(res));
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if (!ctrl->apc0_pll_ctl_addr) {
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dev_err(dev, "Failed to map APC0 PLL CTL register\n");
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ret = -ENOMEM;
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goto free_events;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"apc1-pll-ctl");
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if (!res) {
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dev_err(dev, "Missing APC1 PLL CTL physical address\n");
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ret = -EINVAL;
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goto free_events;
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}
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ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
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res->start,
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resource_size(res));
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if (!ctrl->apc1_pll_ctl_addr) {
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dev_err(dev, "Failed to map APC1 PLL CTL register\n");
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ret = -ENOMEM;
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goto free_events;
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}
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return ret;
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free_events:
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devm_kfree(dev, ctrl->apcs_spm_events_addr);
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return ret;
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}
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static int msm_apm_secure_clock_source_override(
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struct msm_apm_ctrl_dev *ctrl_dev, bool enable)
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{
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int ret;
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if (ctrl_dev->clk_src_override) {
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ret = __invoke_psci_fn_smc(0xC4000020, 3, enable ?
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CLOCK_ASSERT_ENABLE :
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CLOCK_ASSERT_DISABLE, 0);
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if (ret)
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dev_err(ctrl_dev->dev, "PSCI request to switch to %s clock source failed\n",
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enable ? "GPLL0" : "original");
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}
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return 0;
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}
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static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
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{
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int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
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u32 regval;
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int ret = 0;
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unsigned long flags;
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mutex_lock(&scm_lmh_lock);
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spin_lock_irqsave(&ctrl_dev->lock, flags);
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ret = msm_apm_secure_clock_source_override(ctrl_dev, true);
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if (ret)
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return ret;
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/* Perform revision-specific programming steps */
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if (ctrl_dev->version < HMSS_VERSION_1P2) {
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/* Clear SPM events */
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for (i = 0; i < SPM_EVENT_NUM; i++)
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writel_relaxed(SPM_EVENT_CLEAR_VAL,
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ctrl_dev->apcs_spm_events_addr[i]);
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udelay(SPM_WAKEUP_DELAY_US);
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/* Switch APC/CBF to GPLL0 clock */
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writel_relaxed(APCS_GFMUXA_SEL_VAL,
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ctrl_dev->apcs_csr_base + APCS_SPARE);
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ndelay(200);
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writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
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ctrl_dev->apc0_pll_ctl_addr);
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ndelay(200);
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writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
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ctrl_dev->apc1_pll_ctl_addr);
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/* Ensure writes complete before proceeding */
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mb();
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}
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/* Switch arrays to MX supply and wait for its completion */
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writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
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APCC_APM_MODE);
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/* Ensure write above completes before delaying */
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mb();
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while (timeout > 0) {
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regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
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if ((regval & MSM_APM_CTL_STS_MASK) ==
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MSM_APM_MX_DONE_VAL)
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break;
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udelay(1);
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timeout--;
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}
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if (timeout == 0) {
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ret = -ETIMEDOUT;
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dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
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regval);
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}
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/* Perform revision-specific programming steps */
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if (ctrl_dev->version < HMSS_VERSION_1P2) {
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/* Switch APC/CBF clocks to original source */
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writel_relaxed(APCS_GFMUXA_DESEL_VAL,
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ctrl_dev->apcs_csr_base + APCS_SPARE);
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ndelay(200);
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writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
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ctrl_dev->apc0_pll_ctl_addr);
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ndelay(200);
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writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
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ctrl_dev->apc1_pll_ctl_addr);
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/* Complete clock source switch before SPM event sequence */
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mb();
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/* Set SPM events */
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for (i = 0; i < SPM_EVENT_NUM; i++)
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writel_relaxed(SPM_EVENT_SET_VAL,
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ctrl_dev->apcs_spm_events_addr[i]);
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}
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ret = msm_apm_secure_clock_source_override(ctrl_dev, false);
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if (ret)
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return ret;
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if (!ret) {
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ctrl_dev->supply = MSM_APM_SUPPLY_MX;
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dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
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}
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spin_unlock_irqrestore(&ctrl_dev->lock, flags);
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mutex_unlock(&scm_lmh_lock);
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return ret;
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}
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static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
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{
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int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
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u32 regval;
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int ret = 0;
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unsigned long flags;
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mutex_lock(&scm_lmh_lock);
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spin_lock_irqsave(&ctrl_dev->lock, flags);
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ret = msm_apm_secure_clock_source_override(ctrl_dev, true);
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if (ret)
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return ret;
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/* Perform revision-specific programming steps */
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if (ctrl_dev->version < HMSS_VERSION_1P2) {
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/* Clear SPM events */
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for (i = 0; i < SPM_EVENT_NUM; i++)
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writel_relaxed(SPM_EVENT_CLEAR_VAL,
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ctrl_dev->apcs_spm_events_addr[i]);
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udelay(SPM_WAKEUP_DELAY_US);
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/* Switch APC/CBF to GPLL0 clock */
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writel_relaxed(APCS_GFMUXA_SEL_VAL,
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ctrl_dev->apcs_csr_base + APCS_SPARE);
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ndelay(200);
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writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
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ctrl_dev->apc0_pll_ctl_addr);
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ndelay(200);
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writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
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ctrl_dev->apc1_pll_ctl_addr);
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/* Ensure previous writes complete before proceeding */
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mb();
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}
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/* Switch arrays to APCC supply and wait for its completion */
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writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
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APCC_APM_MODE);
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/* Ensure write above completes before delaying */
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mb();
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while (timeout > 0) {
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regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
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if ((regval & MSM_APM_CTL_STS_MASK) ==
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MSM_APM_APCC_DONE_VAL)
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break;
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udelay(1);
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timeout--;
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}
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if (timeout == 0) {
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ret = -ETIMEDOUT;
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dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
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regval);
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}
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/* Perform revision-specific programming steps */
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if (ctrl_dev->version < HMSS_VERSION_1P2) {
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/* Set SPM events */
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for (i = 0; i < SPM_EVENT_NUM; i++)
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writel_relaxed(SPM_EVENT_SET_VAL,
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ctrl_dev->apcs_spm_events_addr[i]);
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/* Complete SPM event sequence before clock source switch */
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mb();
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/* Switch APC/CBF clocks to original source */
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writel_relaxed(APCS_GFMUXA_DESEL_VAL,
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ctrl_dev->apcs_csr_base + APCS_SPARE);
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ndelay(200);
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writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
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ctrl_dev->apc0_pll_ctl_addr);
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ndelay(200);
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writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
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ctrl_dev->apc1_pll_ctl_addr);
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}
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ret = msm_apm_secure_clock_source_override(ctrl_dev, false);
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if (ret)
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return ret;
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if (!ret) {
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ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
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dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
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}
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spin_unlock_irqrestore(&ctrl_dev->lock, flags);
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mutex_unlock(&scm_lmh_lock);
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return ret;
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}
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/**
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* msm_apm_get_supply() - Returns the supply that is currently
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* powering the memory arrays
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* @ctrl_dev: Pointer to an MSM APM controller device
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*
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* Returns the supply currently selected by the APM.
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*/
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int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
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{
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return ctrl_dev->supply;
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}
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EXPORT_SYMBOL(msm_apm_get_supply);
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/**
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* msm_apm_set_supply() - Perform the necessary steps to switch the voltage
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* source of the memory arrays to a given supply
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* @ctrl_dev: Pointer to an MSM APM controller device
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* @supply: Power rail to use as supply for the memory
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* arrays
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*
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* Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
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* the supply is not supported.
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*/
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int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
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enum msm_apm_supply supply)
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{
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int ret;
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switch (supply) {
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case MSM_APM_SUPPLY_APCC:
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ret = msm_apm_switch_to_apcc(ctrl_dev);
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break;
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case MSM_APM_SUPPLY_MX:
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ret = msm_apm_switch_to_mx(ctrl_dev);
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break;
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default:
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ret = -EPERM;
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break;
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}
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return ret;
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}
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EXPORT_SYMBOL(msm_apm_set_supply);
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/**
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* msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
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* the device in device tree
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|
* @dev: Pointer to the device
|
|
*
|
|
* The device must specify "qcom,apm-ctrl" property in its device tree
|
|
* node which points to an MSM APM controller device node.
|
|
*
|
|
* Returns an MSM APM controller handle if successful or ERR_PTR on any error.
|
|
* If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
|
|
* returned.
|
|
*/
|
|
struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
|
|
{
|
|
struct msm_apm_ctrl_dev *ctrl_dev = NULL;
|
|
struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
|
|
struct device_node *ctrl_node;
|
|
|
|
if (!dev || !dev->of_node) {
|
|
pr_err("Invalid device node\n");
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
|
|
if (!ctrl_node) {
|
|
pr_err("Could not find qcom,apm-ctrl property in %s\n",
|
|
dev->of_node->full_name);
|
|
return ERR_PTR(-ENXIO);
|
|
}
|
|
|
|
mutex_lock(&apm_ctrl_list_mutex);
|
|
list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
|
|
if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
|
|
dev_found = ctrl_dev;
|
|
break;
|
|
}
|
|
}
|
|
mutex_unlock(&apm_ctrl_list_mutex);
|
|
|
|
of_node_put(ctrl_node);
|
|
return dev_found;
|
|
}
|
|
EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
|
|
{
|
|
filep->private_data = inode->i_private;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
|
|
size_t count, loff_t *ppos)
|
|
{
|
|
struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
|
|
char buf[10];
|
|
int len;
|
|
|
|
if (!ctrl_dev) {
|
|
pr_err("invalid apm ctrl handle\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
|
|
len = snprintf(buf, sizeof(buf), "APCC\n");
|
|
else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
|
|
len = snprintf(buf, sizeof(buf), "MX\n");
|
|
else
|
|
len = snprintf(buf, sizeof(buf), "ERR\n");
|
|
|
|
return simple_read_from_buffer(ubuf, count, ppos, buf, len);
|
|
}
|
|
|
|
static const struct file_operations apm_supply_fops = {
|
|
.open = apm_supply_dbg_open,
|
|
.read = apm_supply_dbg_read,
|
|
};
|
|
|
|
static void apm_debugfs_base_init(void)
|
|
{
|
|
apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
|
|
|
|
if (IS_ERR_OR_NULL(apm_debugfs_base))
|
|
pr_err("msm-apm debugfs base directory creation failed\n");
|
|
}
|
|
|
|
static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
|
|
{
|
|
struct dentry *temp;
|
|
|
|
if (IS_ERR_OR_NULL(apm_debugfs_base)) {
|
|
pr_err("Base directory missing, cannot create apm debugfs nodes\n");
|
|
return;
|
|
}
|
|
|
|
ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
|
|
apm_debugfs_base);
|
|
if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
|
|
pr_err("%s debugfs directory creation failed\n",
|
|
dev_name(ctrl_dev->dev));
|
|
return;
|
|
}
|
|
|
|
temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
|
|
ctrl_dev, &apm_supply_fops);
|
|
if (IS_ERR_OR_NULL(temp)) {
|
|
pr_err("supply mode creation failed\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
|
|
{
|
|
if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
|
|
debugfs_remove_recursive(ctrl_dev->debugfs);
|
|
}
|
|
|
|
static void apm_debugfs_base_remove(void)
|
|
{
|
|
debugfs_remove_recursive(apm_debugfs_base);
|
|
}
|
|
#else
|
|
|
|
static void apm_debugfs_base_init(void)
|
|
{}
|
|
|
|
static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
|
|
{}
|
|
|
|
static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
|
|
{}
|
|
|
|
static void apm_debugfs_base_remove(void)
|
|
{}
|
|
|
|
#endif
|
|
|
|
static int msm_apm_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct msm_apm_ctrl_dev *ctrl;
|
|
int ret = 0;
|
|
|
|
dev_dbg(dev, "probing MSM Array Power Mux driver\n");
|
|
|
|
if (!dev->of_node) {
|
|
dev_err(dev, "Device tree node is missing\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl) {
|
|
dev_err(dev, "MSM APM controller memory allocation failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&ctrl->list);
|
|
spin_lock_init(&ctrl->lock);
|
|
ctrl->dev = dev;
|
|
platform_set_drvdata(pdev, ctrl);
|
|
|
|
ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to add APM controller device\n");
|
|
return ret;
|
|
}
|
|
|
|
apm_debugfs_init(ctrl);
|
|
mutex_lock(&apm_ctrl_list_mutex);
|
|
list_add_tail(&ctrl->list, &apm_ctrl_list);
|
|
mutex_unlock(&apm_ctrl_list_mutex);
|
|
|
|
dev_dbg(dev, "MSM Array Power Mux driver probe successful");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int msm_apm_remove(struct platform_device *pdev)
|
|
{
|
|
struct msm_apm_ctrl_dev *ctrl_dev;
|
|
|
|
ctrl_dev = platform_get_drvdata(pdev);
|
|
if (ctrl_dev) {
|
|
mutex_lock(&apm_ctrl_list_mutex);
|
|
list_del(&ctrl_dev->list);
|
|
mutex_unlock(&apm_ctrl_list_mutex);
|
|
apm_debugfs_deinit(ctrl_dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id msm_apm_match_table[] = {
|
|
{ .compatible = MSM_APM_DRIVER_NAME, },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver msm_apm_driver = {
|
|
.driver = {
|
|
.name = MSM_APM_DRIVER_NAME,
|
|
.of_match_table = msm_apm_match_table,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = msm_apm_probe,
|
|
.remove = msm_apm_remove,
|
|
};
|
|
|
|
static int __init msm_apm_init(void)
|
|
{
|
|
apm_debugfs_base_init();
|
|
return platform_driver_register(&msm_apm_driver);
|
|
}
|
|
|
|
static void __exit msm_apm_exit(void)
|
|
{
|
|
platform_driver_unregister(&msm_apm_driver);
|
|
apm_debugfs_base_remove();
|
|
}
|
|
|
|
arch_initcall(msm_apm_init);
|
|
module_exit(msm_apm_exit);
|
|
|
|
MODULE_DESCRIPTION("MSM Array Power Mux driver");
|
|
MODULE_LICENSE("GPL v2");
|