458 lines
10 KiB
C
458 lines
10 KiB
C
/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "dbm.h"
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/**
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* USB DBM Hardware registers.
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*
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*/
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#define DBM_EP_CFG(n) (0x00 + 4 * (n))
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#define DBM_DATA_FIFO(n) (0x10 + 4 * (n))
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#define DBM_DATA_FIFO_SIZE(n) (0x20 + 4 * (n))
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#define DBM_DATA_FIFO_EN (0x30)
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#define DBM_GEVNTADR (0x34)
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#define DBM_GEVNTSIZ (0x38)
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#define DBM_DBG_CNFG (0x3C)
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#define DBM_HW_TRB0_EP(n) (0x40 + 4 * (n))
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#define DBM_HW_TRB1_EP(n) (0x50 + 4 * (n))
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#define DBM_HW_TRB2_EP(n) (0x60 + 4 * (n))
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#define DBM_HW_TRB3_EP(n) (0x70 + 4 * (n))
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#define DBM_PIPE_CFG (0x80)
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#define DBM_SOFT_RESET (0x84)
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#define DBM_GEN_CFG (0x88)
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#define DBM_GEVNTADR_LSB (0x98)
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#define DBM_GEVNTADR_MSB (0x9C)
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#define DBM_DATA_FIFO_LSB(n) (0xA0 + 8 * (n))
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#define DBM_DATA_FIFO_MSB(n) (0xA4 + 8 * (n))
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#define DBM_1_4_NUM_EP 4
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struct dbm_data {
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void __iomem *base;
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int dbm_num_eps;
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u8 ep_num_mapping[DBM_1_4_NUM_EP];
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};
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static struct dbm_data *dbm_data;
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/**
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* Write register masked field with debug info.
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*
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* @base - DWC3 base virtual address.
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* @offset - register offset.
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* @mask - register bitmask.
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* @val - value to write.
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*
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*/
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static inline void msm_dbm_write_reg_field(void *base, u32 offset,
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const u32 mask, u32 val)
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{
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u32 shift = find_first_bit((void *)&mask, 32);
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u32 tmp = ioread32(base + offset);
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tmp &= ~mask; /* clear written bits */
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val = tmp | (val << shift);
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iowrite32(val, base + offset);
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}
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/**
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*
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* Read register with debug info.
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*
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* @base - DWC3 base virtual address.
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* @offset - register offset.
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*
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* @return u32
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*/
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static inline u32 msm_dbm_read_reg(void *base, u32 offset)
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{
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u32 val = ioread32(base + offset);
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return val;
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}
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/**
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*
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* Write register with debug info.
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*
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* @base - DWC3 base virtual address.
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* @offset - register offset.
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* @val - value to write.
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*
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*/
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static inline void msm_dbm_write_reg(void *base, u32 offset, u32 val)
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{
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iowrite32(val, base + offset);
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}
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/**
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* Return DBM EP number according to usb endpoint number.
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*
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*/
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static int msm_dbm_find_matching_dbm_ep(u8 usb_ep)
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{
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int i;
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for (i = 0; i < dbm_data->dbm_num_eps; i++)
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if (dbm_data->ep_num_mapping[i] == usb_ep)
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return i;
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pr_err("%s: No DBM EP matches USB EP %d", __func__, usb_ep);
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return -ENODEV; /* Not found */
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}
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/**
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* Reset the DBM registers upon initialization.
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*
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*/
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static int soft_reset(bool reset)
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{
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pr_debug("%s DBM reset\n", (reset ? "Enter" : "Exit"));
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msm_dbm_write_reg_field(dbm_data->base, DBM_SOFT_RESET,
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DBM_SFT_RST_MASK, reset);
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return 0;
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}
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/**
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* Soft reset specific DBM ep.
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* This function is called by the function driver upon events
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* such as transfer aborting, USB re-enumeration and USB
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* disconnection.
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*
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* @dbm_ep - DBM ep number.
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* @enter_reset - should we enter a reset state or get out of it.
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*
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*/
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static int ep_soft_reset(u8 dbm_ep, bool enter_reset)
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{
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pr_debug("Setting DBM ep %d reset to %d\n", dbm_ep, enter_reset);
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if (dbm_ep >= dbm_data->dbm_num_eps) {
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pr_err("Invalid DBM ep index %d\n", dbm_ep);
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return -ENODEV;
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}
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if (enter_reset) {
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msm_dbm_write_reg_field(dbm_data->base, DBM_SOFT_RESET,
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DBM_SFT_RST_EPS_MASK & 1 << dbm_ep, 1);
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} else {
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msm_dbm_write_reg_field(dbm_data->base, DBM_SOFT_RESET,
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DBM_SFT_RST_EPS_MASK & 1 << dbm_ep, 0);
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}
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return 0;
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}
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/**
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* Soft reset specific DBM ep (by USB EP number).
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* This function is called by the function driver upon events
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* such as transfer aborting, USB re-enumeration and USB
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* disconnection.
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*
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* The function relies on ep_soft_reset() for checking
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* the legality of the resulting DBM ep number.
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*
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* @usb_ep - USB ep number.
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* @enter_reset - should we enter a reset state or get out of it.
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*
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*/
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static int usb_ep_soft_reset(u8 usb_ep, bool enter_reset)
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{
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int dbm_ep = msm_dbm_find_matching_dbm_ep(usb_ep);
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pr_debug("Setting USB ep %d reset to %d\n", usb_ep, enter_reset);
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return ep_soft_reset(dbm_ep, enter_reset);
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}
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/**
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* Configure a USB DBM ep to work in BAM mode.
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*
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*
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* @usb_ep - USB physical EP number.
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* @producer - producer/consumer.
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* @disable_wb - disable write back to system memory.
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* @internal_mem - use internal USB memory for data fifo.
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* @ioc - enable interrupt on completion.
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*
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* @return int - DBM ep number.
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*/
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static int ep_config(u8 usb_ep, u8 bam_pipe, bool producer, bool disable_wb,
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bool internal_mem, bool ioc)
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{
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int dbm_ep;
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u32 ep_cfg;
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pr_debug("Configuring DBM ep\n");
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dbm_ep = msm_dbm_find_matching_dbm_ep(usb_ep);
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if (dbm_ep < 0) {
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pr_err("usb ep index %d has no corresponding dbm ep\n", usb_ep);
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return -ENODEV;
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}
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/* First, reset the dbm endpoint */
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ep_soft_reset(dbm_ep, 0);
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/* Set ioc bit for dbm_ep if needed */
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msm_dbm_write_reg_field(dbm_data->base, DBM_DBG_CNFG,
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DBM_ENABLE_IOC_MASK & 1 << dbm_ep, ioc ? 1 : 0);
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ep_cfg = (producer ? DBM_PRODUCER : 0) |
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(disable_wb ? DBM_DISABLE_WB : 0) |
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(internal_mem ? DBM_INT_RAM_ACC : 0);
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msm_dbm_write_reg_field(dbm_data->base, DBM_EP_CFG(dbm_ep),
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DBM_PRODUCER | DBM_DISABLE_WB | DBM_INT_RAM_ACC, ep_cfg >> 8);
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msm_dbm_write_reg_field(dbm_data->base, DBM_EP_CFG(dbm_ep), USB3_EPNUM,
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usb_ep);
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msm_dbm_write_reg_field(dbm_data->base, DBM_EP_CFG(dbm_ep),
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DBM_BAM_PIPE_NUM, bam_pipe);
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msm_dbm_write_reg_field(dbm_data->base, DBM_PIPE_CFG, 0x000000ff,
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0xe4);
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msm_dbm_write_reg_field(dbm_data->base, DBM_EP_CFG(dbm_ep), DBM_EN_EP,
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1);
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return dbm_ep;
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}
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/**
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* Configure a USB DBM ep to work in normal mode.
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*
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* @usb_ep - USB ep number.
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*
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*/
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static int ep_unconfig(u8 usb_ep)
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{
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int dbm_ep;
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u32 data;
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pr_debug("Unconfiguring DB ep\n");
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dbm_ep = msm_dbm_find_matching_dbm_ep(usb_ep);
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if (dbm_ep < 0) {
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pr_err("usb ep index %d has no corresponding dbm ep\n", usb_ep);
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return -ENODEV;
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}
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dbm_data->ep_num_mapping[dbm_ep] = 0;
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data = msm_dbm_read_reg(dbm_data->base, DBM_EP_CFG(dbm_ep));
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data &= (~0x1);
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msm_dbm_write_reg(dbm_data->base, DBM_EP_CFG(dbm_ep), data);
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/* Reset the dbm endpoint */
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ep_soft_reset(dbm_ep, true);
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/*
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* 10 usec delay is required before deasserting DBM endpoint reset
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* according to hardware programming guide.
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*/
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udelay(10);
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ep_soft_reset(dbm_ep, false);
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return 0;
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}
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/**
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* Return number of configured DBM endpoints.
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*
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*/
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static int get_num_of_eps_configured(void)
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{
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int i;
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int count = 0;
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for (i = 0; i < dbm_data->dbm_num_eps; i++)
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if (dbm_data->ep_num_mapping[i])
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count++;
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return count;
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}
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/**
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* Configure the DBM with the USB3 core event buffer.
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* This function is called by the SNPS UDC upon initialization.
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*
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* @addr - address of the event buffer.
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* @size - size of the event buffer.
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*
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*/
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static int event_buffer_config(u32 addr_lo, u32 addr_hi, int size)
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{
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pr_debug("Configuring event buffer\n");
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if (size < 0) {
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pr_err("Invalid size. size = %d", size);
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return -EINVAL;
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}
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if (sizeof(phys_addr_t) > sizeof(u32)) {
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msm_dbm_write_reg(dbm_data->base, DBM_GEVNTADR_LSB, addr_lo);
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msm_dbm_write_reg(dbm_data->base, DBM_GEVNTADR_MSB, addr_hi);
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} else {
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msm_dbm_write_reg(dbm_data->base, DBM_GEVNTADR, addr_lo);
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}
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msm_dbm_write_reg_field(dbm_data->base, DBM_GEVNTSIZ,
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DBM_GEVNTSIZ_MASK, size);
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return 0;
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}
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static int data_fifo_config(u8 dep_num, phys_addr_t addr,
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u32 size, u8 dst_pipe_idx)
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{
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u8 dbm_ep;
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dbm_ep = dst_pipe_idx;
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dbm_data->ep_num_mapping[dbm_ep] = dep_num;
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if (sizeof(addr) > sizeof(u32)) {
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u32 lo = lower_32_bits(addr);
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u32 hi = upper_32_bits(addr);
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msm_dbm_write_reg(dbm_data->base,
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DBM_DATA_FIFO_LSB(dbm_ep), lo);
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msm_dbm_write_reg(dbm_data->base,
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DBM_DATA_FIFO_MSB(dbm_ep), hi);
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} else {
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msm_dbm_write_reg(dbm_data->base,
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DBM_DATA_FIFO(dbm_ep), addr);
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}
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msm_dbm_write_reg_field(dbm_data->base, DBM_DATA_FIFO_SIZE(dbm_ep),
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DBM_DATA_FIFO_SIZE_MASK, size);
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return 0;
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}
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static void set_speed(bool speed)
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{
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msm_dbm_write_reg(dbm_data->base, DBM_GEN_CFG, speed);
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}
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static bool reset_ep_after_lpm(void)
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{
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return false;
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}
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static void enable(void) {}
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static int msm_dbm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dbm *dbm;
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struct resource *res;
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int ret = 0;
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dbm_data = devm_kzalloc(dev, sizeof(*dbm_data), GFP_KERNEL);
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if (!dbm_data)
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return -ENOMEM;
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dbm_data->dbm_num_eps = DBM_1_4_NUM_EP;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "missing memory base resource\n");
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ret = -ENODEV;
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goto free_dbm_data;
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}
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dbm_data->base = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!dbm_data->base) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto free_dbm_data;
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}
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dbm = devm_kzalloc(dev, sizeof(*dbm), GFP_KERNEL);
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if (!dbm) {
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dev_err(&pdev->dev, "not enough memory\n");
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ret = -ENOMEM;
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goto free_dbm_data;
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}
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dbm->dev = dev;
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dbm->soft_reset = soft_reset;
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dbm->ep_config = ep_config;
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dbm->ep_unconfig = ep_unconfig;
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dbm->get_num_of_eps_configured = get_num_of_eps_configured;
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dbm->event_buffer_config = event_buffer_config;
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dbm->data_fifo_config = data_fifo_config;
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dbm->set_speed = set_speed;
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dbm->enable = enable;
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dbm->ep_soft_reset = usb_ep_soft_reset;
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dbm->reset_ep_after_lpm = reset_ep_after_lpm;
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platform_set_drvdata(pdev, dbm);
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return usb_add_dbm(dbm);
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free_dbm_data:
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kfree(dbm_data);
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return ret;
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}
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static int msm_dbm_remove(struct platform_device *pdev)
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{
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struct dbm *dbm = platform_get_drvdata(pdev);
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kfree(dbm);
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kfree(dbm_data);
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return 0;
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}
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static const struct of_device_id msm_dbm_1_4_id_table[] = {
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{
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.compatible = "qcom,usb-dbm-1p4",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, msm_dbm_1_4_id_table);
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static struct platform_driver msm_dbm_driver = {
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.probe = msm_dbm_probe,
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.remove = msm_dbm_remove,
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.driver = {
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.name = "msm-usb-dbm-1-4",
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.of_match_table = of_match_ptr(msm_dbm_1_4_id_table),
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},
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};
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module_platform_driver(msm_dbm_driver);
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MODULE_DESCRIPTION("MSM USB DBM 1.4 driver");
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MODULE_LICENSE("GPL v2");
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