469 lines
13 KiB
C
469 lines
13 KiB
C
/*
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* coh901327_wdt.c
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*
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* Copyright (C) 2008-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include <linux/interrupt.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#define DRV_NAME "WDOG COH 901 327"
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/*
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* COH 901 327 register definitions
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*/
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/* WDOG_FEED Register 32bit (-/W) */
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#define U300_WDOG_FR 0x00
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#define U300_WDOG_FR_FEED_RESTART_TIMER 0xFEEDU
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/* WDOG_TIMEOUT Register 32bit (R/W) */
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#define U300_WDOG_TR 0x04
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#define U300_WDOG_TR_TIMEOUT_MASK 0x7FFFU
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/* WDOG_DISABLE1 Register 32bit (-/W) */
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#define U300_WDOG_D1R 0x08
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#define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER 0x2BADU
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/* WDOG_DISABLE2 Register 32bit (R/W) */
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#define U300_WDOG_D2R 0x0C
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#define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER 0xCAFEU
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#define U300_WDOG_D2R_DISABLE_STATUS_DISABLED 0xDABEU
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#define U300_WDOG_D2R_DISABLE_STATUS_ENABLED 0x0000U
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/* WDOG_STATUS Register 32bit (R/W) */
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#define U300_WDOG_SR 0x10
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#define U300_WDOG_SR_STATUS_TIMED_OUT 0xCFE8U
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#define U300_WDOG_SR_STATUS_NORMAL 0x0000U
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#define U300_WDOG_SR_RESET_STATUS_RESET 0xE8B4U
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/* WDOG_COUNT Register 32bit (R/-) */
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#define U300_WDOG_CR 0x14
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#define U300_WDOG_CR_VALID_IND 0x8000U
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#define U300_WDOG_CR_VALID_STABLE 0x0000U
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#define U300_WDOG_CR_COUNT_VALUE_MASK 0x7FFFU
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/* WDOG_JTAGOVR Register 32bit (R/W) */
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#define U300_WDOG_JOR 0x18
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#define U300_WDOG_JOR_JTAG_MODE_IND 0x0002U
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#define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE 0x0001U
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/* WDOG_RESTART Register 32bit (-/W) */
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#define U300_WDOG_RR 0x1C
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#define U300_WDOG_RR_RESTART_VALUE_RESUME 0xACEDU
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/* WDOG_IRQ_EVENT Register 32bit (R/W) */
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#define U300_WDOG_IER 0x20
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#define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND 0x0001U
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#define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE 0x0001U
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/* WDOG_IRQ_MASK Register 32bit (R/W) */
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#define U300_WDOG_IMR 0x24
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#define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE 0x0001U
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/* WDOG_IRQ_FORCE Register 32bit (R/W) */
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#define U300_WDOG_IFR 0x28
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#define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE 0x0001U
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/* Default timeout in seconds = 1 minute */
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static unsigned int margin = 60;
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static resource_size_t phybase;
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static resource_size_t physize;
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static int irq;
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static void __iomem *virtbase;
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static struct device *parent;
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/*
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* The watchdog block is of course always clocked, the
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* clk_enable()/clk_disable() calls are mainly for performing reference
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* counting higher up in the clock hierarchy.
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*/
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static struct clk *clk;
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/*
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* Enabling and disabling functions.
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*/
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static void coh901327_enable(u16 timeout)
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{
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u16 val;
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unsigned long freq;
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unsigned long delay_ns;
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clk_enable(clk);
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/* Restart timer if it is disabled */
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val = readw(virtbase + U300_WDOG_D2R);
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if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
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writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
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virtbase + U300_WDOG_RR);
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/* Acknowledge any pending interrupt so it doesn't just fire off */
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writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
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virtbase + U300_WDOG_IER);
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/*
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* The interrupt is cleared in the 32 kHz clock domain.
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* Wait 3 32 kHz cycles for it to take effect
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*/
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freq = clk_get_rate(clk);
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delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
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delay_ns = 3 * delay_ns; /* Wait 3 cycles */
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ndelay(delay_ns);
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/* Enable the watchdog interrupt */
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writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
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/* Activate the watchdog timer */
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writew(timeout, virtbase + U300_WDOG_TR);
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/* Start the watchdog timer */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
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/*
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* Extra read so that this change propagate in the watchdog.
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*/
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(void) readw(virtbase + U300_WDOG_CR);
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val = readw(virtbase + U300_WDOG_D2R);
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clk_disable(clk);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
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dev_err(parent,
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"%s(): watchdog not enabled! D2R value %04x\n",
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__func__, val);
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}
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static void coh901327_disable(void)
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{
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u16 val;
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clk_enable(clk);
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/* Disable the watchdog interrupt if it is active */
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writew(0x0000U, virtbase + U300_WDOG_IMR);
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/* If the watchdog is currently enabled, attempt to disable it */
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val = readw(virtbase + U300_WDOG_D2R);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
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writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
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virtbase + U300_WDOG_D1R);
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writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
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virtbase + U300_WDOG_D2R);
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/* Write this twice (else problems occur) */
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writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
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virtbase + U300_WDOG_D2R);
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}
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val = readw(virtbase + U300_WDOG_D2R);
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clk_disable(clk);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
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dev_err(parent,
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"%s(): watchdog not disabled! D2R value %04x\n",
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__func__, val);
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}
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static int coh901327_start(struct watchdog_device *wdt_dev)
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{
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coh901327_enable(wdt_dev->timeout * 100);
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return 0;
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}
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static int coh901327_stop(struct watchdog_device *wdt_dev)
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{
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coh901327_disable();
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return 0;
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}
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static int coh901327_ping(struct watchdog_device *wdd)
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{
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clk_enable(clk);
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/* Feed the watchdog */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER,
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virtbase + U300_WDOG_FR);
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clk_disable(clk);
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return 0;
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}
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static int coh901327_settimeout(struct watchdog_device *wdt_dev,
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unsigned int time)
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{
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wdt_dev->timeout = time;
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clk_enable(clk);
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/* Set new timeout value */
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writew(time * 100, virtbase + U300_WDOG_TR);
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/* Feed the dog */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER,
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virtbase + U300_WDOG_FR);
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clk_disable(clk);
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return 0;
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}
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static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
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{
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u16 val;
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clk_enable(clk);
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/* Read repeatedly until the value is stable! */
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val = readw(virtbase + U300_WDOG_CR);
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while (val & U300_WDOG_CR_VALID_IND)
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val = readw(virtbase + U300_WDOG_CR);
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val &= U300_WDOG_CR_COUNT_VALUE_MASK;
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clk_disable(clk);
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if (val != 0)
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val /= 100;
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return val;
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}
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/*
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* This interrupt occurs 10 ms before the watchdog WILL bark.
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*/
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static irqreturn_t coh901327_interrupt(int irq, void *data)
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{
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u16 val;
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/*
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* Ack IRQ? If this occurs we're FUBAR anyway, so
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* just acknowledge, disable the interrupt and await the imminent end.
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* If you at some point need a host of callbacks to be called
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* when the system is about to watchdog-reset, add them here!
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*
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* NOTE: on future versions of this IP-block, it will be possible
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* to prevent a watchdog reset by feeding the watchdog at this
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* point.
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*/
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clk_enable(clk);
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val = readw(virtbase + U300_WDOG_IER);
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if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
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writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
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virtbase + U300_WDOG_IER);
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writew(0x0000U, virtbase + U300_WDOG_IMR);
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clk_disable(clk);
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dev_crit(parent, "watchdog is barking!\n");
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return IRQ_HANDLED;
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}
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static const struct watchdog_info coh901327_ident = {
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.options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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.identity = DRV_NAME,
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};
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static struct watchdog_ops coh901327_ops = {
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.owner = THIS_MODULE,
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.start = coh901327_start,
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.stop = coh901327_stop,
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.ping = coh901327_ping,
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.set_timeout = coh901327_settimeout,
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.get_timeleft = coh901327_gettimeleft,
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};
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static struct watchdog_device coh901327_wdt = {
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.info = &coh901327_ident,
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.ops = &coh901327_ops,
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/*
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* Max timeout is 327 since the 10ms
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* timeout register is max
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* 0x7FFF = 327670ms ~= 327s.
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*/
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.min_timeout = 0,
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.max_timeout = 327,
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};
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static int __exit coh901327_remove(struct platform_device *pdev)
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{
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watchdog_unregister_device(&coh901327_wdt);
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coh901327_disable();
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free_irq(irq, pdev);
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clk_unprepare(clk);
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clk_put(clk);
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iounmap(virtbase);
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release_mem_region(phybase, physize);
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return 0;
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}
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static int __init coh901327_probe(struct platform_device *pdev)
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{
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int ret;
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u16 val;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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parent = &pdev->dev;
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physize = resource_size(res);
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phybase = res->start;
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if (request_mem_region(phybase, physize, DRV_NAME) == NULL) {
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ret = -EBUSY;
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goto out;
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}
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virtbase = ioremap(phybase, physize);
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if (!virtbase) {
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ret = -ENOMEM;
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goto out_no_remap;
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}
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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dev_err(&pdev->dev, "could not get clock\n");
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goto out_no_clk;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "could not prepare and enable clock\n");
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goto out_no_clk_enable;
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}
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val = readw(virtbase + U300_WDOG_SR);
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switch (val) {
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case U300_WDOG_SR_STATUS_TIMED_OUT:
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dev_info(&pdev->dev,
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"watchdog timed out since last chip reset!\n");
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coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
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/* Status will be cleared below */
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break;
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case U300_WDOG_SR_STATUS_NORMAL:
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dev_info(&pdev->dev,
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"in normal status, no timeouts have occurred.\n");
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break;
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default:
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dev_info(&pdev->dev,
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"contains an illegal status code (%08x)\n", val);
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break;
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}
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val = readw(virtbase + U300_WDOG_D2R);
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switch (val) {
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case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
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dev_info(&pdev->dev, "currently disabled.\n");
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break;
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case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
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dev_info(&pdev->dev,
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"currently enabled! (disabling it now)\n");
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coh901327_disable();
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break;
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default:
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dev_err(&pdev->dev,
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"contains an illegal enable/disable code (%08x)\n",
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val);
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break;
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}
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/* Reset the watchdog */
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writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
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irq = platform_get_irq(pdev, 0);
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if (request_irq(irq, coh901327_interrupt, 0,
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DRV_NAME " Bark", pdev)) {
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ret = -EIO;
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goto out_no_irq;
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}
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clk_disable(clk);
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ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
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if (ret < 0)
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coh901327_wdt.timeout = 60;
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ret = watchdog_register_device(&coh901327_wdt);
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if (ret == 0)
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dev_info(&pdev->dev,
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"initialized. timer margin=%d sec\n", margin);
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else
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goto out_no_wdog;
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return 0;
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out_no_wdog:
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free_irq(irq, pdev);
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out_no_irq:
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clk_disable_unprepare(clk);
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out_no_clk_enable:
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clk_put(clk);
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out_no_clk:
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iounmap(virtbase);
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out_no_remap:
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release_mem_region(phybase, SZ_4K);
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out:
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return ret;
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}
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#ifdef CONFIG_PM
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static u16 wdogenablestore;
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static u16 irqmaskstore;
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static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
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{
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irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
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wdogenablestore = readw(virtbase + U300_WDOG_D2R);
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/* If watchdog is on, disable it here and now */
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if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
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coh901327_disable();
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return 0;
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}
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static int coh901327_resume(struct platform_device *pdev)
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{
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/* Restore the watchdog interrupt */
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writew(irqmaskstore, virtbase + U300_WDOG_IMR);
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if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
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/* Restart the watchdog timer */
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writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
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virtbase + U300_WDOG_RR);
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writew(U300_WDOG_FR_FEED_RESTART_TIMER,
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virtbase + U300_WDOG_FR);
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}
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return 0;
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}
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#else
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#define coh901327_suspend NULL
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#define coh901327_resume NULL
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#endif
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/*
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* Mistreating the watchdog is the only way to perform a software reset of the
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* system on EMP platforms. So we implement this and export a symbol for it.
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*/
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void coh901327_watchdog_reset(void)
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{
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/* Enable even if on JTAG too */
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writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
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virtbase + U300_WDOG_JOR);
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/*
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* Timeout = 5s, we have to wait for the watchdog reset to
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* actually take place: the watchdog will be reloaded with the
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* default value immediately, so we HAVE to reboot and get back
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* into the kernel in 30s, or the device will reboot again!
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* The boot loader will typically deactivate the watchdog, so we
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* need time enough for the boot loader to get to the point of
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* deactivating the watchdog before it is shut down by it.
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*
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* NOTE: on future versions of the watchdog, this restriction is
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* gone: the watchdog will be reloaded with a default value (1 min)
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* instead of last value, and you can conveniently set the watchdog
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* timeout to 10ms (value = 1) without any problems.
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*/
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coh901327_enable(500);
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/* Return and await doom */
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}
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static const struct of_device_id coh901327_dt_match[] = {
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{ .compatible = "stericsson,coh901327" },
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{},
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};
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static struct platform_driver coh901327_driver = {
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.driver = {
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.owner = THIS_MODULE,
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.name = "coh901327_wdog",
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.of_match_table = coh901327_dt_match,
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},
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.remove = __exit_p(coh901327_remove),
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.suspend = coh901327_suspend,
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.resume = coh901327_resume,
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};
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module_platform_driver_probe(coh901327_driver, coh901327_probe);
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MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
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MODULE_DESCRIPTION("COH 901 327 Watchdog");
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module_param(margin, uint, 0);
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MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:coh901327-watchdog");
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