196 lines
4.1 KiB
Text
196 lines
4.1 KiB
Text
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,acc = <&acc0>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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power-domain = <&l2ccc_1>;
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};
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile1>;
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qcom,acc = <&acc1>;
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next-level-cache = <&L2_1>;
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile2>;
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qcom,acc = <&acc2>;
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next-level-cache = <&L2_1>;
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile3>;
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qcom,acc = <&acc3>;
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next-level-cache = <&L2_1>;
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};
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CPU4: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile4>;
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qcom,acc = <&acc4>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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power-domain = <&l2ccc_0>;
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};
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};
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CPU5: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile4>;
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qcom,acc = <&acc5>;
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next-level-cache = <&L2_0>;
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};
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CPU6: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile4>;
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qcom,acc = <&acc6>;
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next-level-cache = <&L2_0>;
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};
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CPU7: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile4>;
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qcom,acc = <&acc7>;
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next-level-cache = <&L2_0>;
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};
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};
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};
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&soc {
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l2ccc_0: clock-controller@b111000 {
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compatible = "qcom,8916-l2ccc";
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reg = <0x0b111000 0x1000>;
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};
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l2ccc_1: clock-controller@b011000 {
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compatible = "qcom,8916-l2ccc";
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reg = <0x0b011000 0x1000>;
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};
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acc0:clock-controller@b088000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b088000 0x1000>;
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};
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acc1:clock-controller@b098000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b098000 0x1000>;
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};
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acc2:clock-controller@b0a8000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b0a8000 0x1000>;
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};
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acc3:clock-controller@b0b8000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b0b8000 0x1000>;
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};
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acc4:clock-controller@b188000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b188000 0x1000>;
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};
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acc5:clock-controller@b198000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b198000 0x1000>;
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};
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acc6:clock-controller@b1a8000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b1a8000 0x1000>;
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};
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acc7:clock-controller@b1b8000 {
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compatible = "qcom,arm-cortex-acc";
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reg = <0x0b1b8000 0x1000>;
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};
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};
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