1443 lines
43 KiB
C
1443 lines
43 KiB
C
/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_MDP_H
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#define MDSS_MDP_H
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#include <linux/io.h>
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#include <linux/msm_mdp.h>
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#include <linux/msm_mdp_ext.h>
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#include <linux/platform_device.h>
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#include <linux/notifier.h>
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#include <linux/irqreturn.h>
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#include <linux/kref.h>
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#include "mdss.h"
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#include "mdss_mdp_hwio.h"
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#include "mdss_fb.h"
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#include "mdss_mdp_cdm.h"
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#define MDSS_MDP_DEFAULT_INTR_MASK 0
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#define PHASE_STEP_SHIFT 21
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#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
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#define PHASE_RESIDUAL 15
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#define MAX_LINE_BUFFER_WIDTH 2048
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#define MAX_MIXER_HEIGHT 0xFFFF
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#define MAX_IMG_WIDTH 0x3FFF
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#define MAX_IMG_HEIGHT 0x3FFF
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#define AHB_CLK_OFFSET 0x2B4
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#define MAX_DST_H MAX_MIXER_HEIGHT
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#define MAX_DOWNSCALE_RATIO 4
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#define MAX_UPSCALE_RATIO 20
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#define MAX_DECIMATION 4
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#define MDP_MIN_VBP 4
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#define MAX_FREE_LIST_SIZE 12
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#define OVERLAY_MAX 10
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#define VALID_ROT_WB_FORMAT BIT(0)
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#define VALID_MDP_WB_INTF_FORMAT BIT(1)
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#define C3_ALPHA 3 /* alpha */
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#define C2_R_Cr 2 /* R/Cr */
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#define C1_B_Cb 1 /* B/Cb */
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#define C0_G_Y 0 /* G/luma */
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/* wait for at most 2 vsync for lowest refresh rate (24hz) */
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#define KOFF_TIMEOUT msecs_to_jiffies(1000)
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#define OVERFETCH_DISABLE_TOP BIT(0)
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#define OVERFETCH_DISABLE_BOTTOM BIT(1)
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#define OVERFETCH_DISABLE_LEFT BIT(2)
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#define OVERFETCH_DISABLE_RIGHT BIT(3)
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#define MDSS_MDP_CDP_ENABLE BIT(0)
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#define MDSS_MDP_CDP_ENABLE_UBWCMETA BIT(1)
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#define MDSS_MDP_CDP_AMORTIZED BIT(2)
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#define MDSS_MDP_CDP_AHEAD_64 BIT(3)
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#define PERF_STATUS_DONE 0
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#define PERF_STATUS_BUSY 1
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#define PERF_CALC_PIPE_APPLY_CLK_FUDGE BIT(0)
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#define PERF_CALC_PIPE_SINGLE_LAYER BIT(1)
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#define PERF_CALC_PIPE_CALC_SMP_SIZE BIT(2)
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#define PERF_SINGLE_PIPE_BW_FLOOR 1200000000
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#define CURSOR_PIPE_LEFT 0
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#define CURSOR_PIPE_RIGHT 1
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#define MASTER_CTX 0
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#define SLAVE_CTX 1
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#define XIN_HALT_TIMEOUT_US 0x4000
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/* hw cursor can only be setup in highest mixer stage */
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#define HW_CURSOR_STAGE(mdata) \
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(((mdata)->max_target_zorder + MDSS_MDP_STAGE_0) - 1)
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enum mdss_mdp_perf_state_type {
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PERF_SW_COMMIT_STATE = 0,
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PERF_HW_MDP_STATE,
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};
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enum mdss_mdp_block_power_state {
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MDP_BLOCK_POWER_OFF = 0,
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MDP_BLOCK_POWER_ON = 1,
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};
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enum mdss_mdp_mixer_type {
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MDSS_MDP_MIXER_TYPE_UNUSED,
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MDSS_MDP_MIXER_TYPE_INTF,
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MDSS_MDP_MIXER_TYPE_WRITEBACK,
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};
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enum mdss_mdp_mixer_mux {
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MDSS_MDP_MIXER_MUX_DEFAULT,
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MDSS_MDP_MIXER_MUX_LEFT,
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MDSS_MDP_MIXER_MUX_RIGHT,
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};
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enum mdss_mdp_pipe_type {
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MDSS_MDP_PIPE_TYPE_UNUSED,
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MDSS_MDP_PIPE_TYPE_VIG,
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MDSS_MDP_PIPE_TYPE_RGB,
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MDSS_MDP_PIPE_TYPE_DMA,
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MDSS_MDP_PIPE_TYPE_CURSOR,
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};
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enum mdss_mdp_block_type {
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MDSS_MDP_BLOCK_UNUSED,
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MDSS_MDP_BLOCK_SSPP,
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MDSS_MDP_BLOCK_MIXER,
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MDSS_MDP_BLOCK_DSPP,
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MDSS_MDP_BLOCK_WB,
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MDSS_MDP_BLOCK_CDM,
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MDSS_MDP_BLOCK_MAX
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};
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enum mdss_mdp_csc_type {
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MDSS_MDP_CSC_YUV2RGB_601L,
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MDSS_MDP_CSC_YUV2RGB_601FR,
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MDSS_MDP_CSC_YUV2RGB_709L,
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MDSS_MDP_CSC_YUV2RGB_2020L,
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MDSS_MDP_CSC_YUV2RGB_2020FR,
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MDSS_MDP_CSC_YUV2RGB_P3L,
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MDSS_MDP_CSC_YUV2RGB_P3FR,
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MDSS_MDP_CSC_RGB2YUV_601L,
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MDSS_MDP_CSC_RGB2YUV_601FR,
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MDSS_MDP_CSC_RGB2YUV_709L,
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MDSS_MDP_CSC_RGB2YUV_2020L,
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MDSS_MDP_CSC_RGB2YUV_2020FR,
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MDSS_MDP_CSC_YUV2YUV,
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MDSS_MDP_CSC_RGB2RGB,
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MDSS_MDP_MAX_CSC
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};
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enum mdp_wfd_blk_type {
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MDSS_MDP_WFD_SHARED = 0,
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MDSS_MDP_WFD_INTERFACE,
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MDSS_MDP_WFD_DEDICATED,
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};
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enum mdss_mdp_reg_bus_cfg {
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REG_CLK_CFG_OFF,
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REG_CLK_CFG_LOW,
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REG_CLK_CFG_HIGH,
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};
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enum mdss_mdp_panic_signal_type {
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MDSS_MDP_PANIC_NONE,
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MDSS_MDP_PANIC_COMMON_REG_CFG,
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MDSS_MDP_PANIC_PER_PIPE_CFG,
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};
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enum mdss_mdp_fetch_type {
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MDSS_MDP_FETCH_LINEAR,
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MDSS_MDP_FETCH_TILE,
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MDSS_MDP_FETCH_UBWC,
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};
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/**
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* enum mdp_commit_stage_type - Indicate different commit stages
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*
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* @MDP_COMMIT_STATE_WAIT_FOR_PINGPONG: At the stage of being ready to
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* wait for pingpong buffer.
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* @MDP_COMMIT_STATE_PINGPONG_DONE: At the stage that pingpong
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* buffer is ready.
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*/
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enum mdp_commit_stage_type {
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MDP_COMMIT_STAGE_SETUP_DONE,
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MDP_COMMIT_STAGE_READY_FOR_KICKOFF,
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};
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struct mdss_mdp_ctl;
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typedef void (*mdp_vsync_handler_t)(struct mdss_mdp_ctl *, ktime_t);
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struct mdss_mdp_vsync_handler {
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bool enabled;
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bool cmd_post_flush;
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mdp_vsync_handler_t vsync_handler;
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struct list_head list;
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};
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enum mdss_mdp_wb_ctl_type {
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MDSS_MDP_WB_CTL_TYPE_BLOCK = 1,
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MDSS_MDP_WB_CTL_TYPE_LINE
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};
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enum mdss_mdp_bw_vote_mode {
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MDSS_MDP_BW_MODE_SINGLE_LAYER,
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MDSS_MDP_BW_MODE_MAX
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};
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enum mdp_wb_blk_caps {
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MDSS_MDP_WB_WFD = BIT(0),
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MDSS_MDP_WB_ROTATOR = BIT(1),
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MDSS_MDP_WB_INTF = BIT(2),
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MDSS_MDP_WB_UBWC = BIT(3),
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};
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struct mdss_mdp_perf_params {
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u64 bw_overlap;
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u64 bw_writeback;
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u64 bw_prefill;
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u64 max_per_pipe_ib;
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u32 prefill_bytes;
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u64 bw_ctl;
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u32 mdp_clk_rate;
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DECLARE_BITMAP(bw_vote_mode, MDSS_MDP_BW_MODE_MAX);
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};
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struct mdss_mdp_writeback {
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u32 num;
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char __iomem *base;
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u32 caps;
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struct kref kref;
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};
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struct mdss_mdp_ctl_intfs_ops {
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int (*start_fnc)(struct mdss_mdp_ctl *ctl);
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int (*stop_fnc)(struct mdss_mdp_ctl *ctl, int panel_power_state);
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int (*prepare_fnc)(struct mdss_mdp_ctl *ctl, void *arg);
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int (*display_fnc)(struct mdss_mdp_ctl *ctl, void *arg);
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int (*wait_fnc)(struct mdss_mdp_ctl *ctl, void *arg);
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int (*wait_pingpong)(struct mdss_mdp_ctl *ctl, void *arg);
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u32 (*read_line_cnt_fnc)(struct mdss_mdp_ctl *);
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int (*add_vsync_handler)(struct mdss_mdp_ctl *,
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struct mdss_mdp_vsync_handler *);
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int (*remove_vsync_handler)(struct mdss_mdp_ctl *,
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struct mdss_mdp_vsync_handler *);
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int (*config_fps_fnc)(struct mdss_mdp_ctl *ctl, int new_fps);
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int (*restore_fnc)(struct mdss_mdp_ctl *ctl, bool locked);
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int (*early_wake_up_fnc)(struct mdss_mdp_ctl *ctl);
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/*
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* reconfigure interface for new resolution, called before (pre=1)
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* and after interface has been reconfigured (pre=0)
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*/
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int (*reconfigure)(struct mdss_mdp_ctl *ctl,
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enum dynamic_switch_modes mode, bool pre);
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/* called before do any register programming from commit thread */
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void (*pre_programming)(struct mdss_mdp_ctl *ctl);
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#if defined(CONFIG_FB_MSM_MDSS_SAMSUNG)
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int (*wait_video_pingpong) (struct mdss_mdp_ctl *ctl, void *arg);
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#endif
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};
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struct mdss_mdp_ctl {
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u32 num;
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char __iomem *base;
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u32 ref_cnt;
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int power_state;
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u32 intf_num;
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u32 slave_intf_num; /* ping-pong split */
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u32 intf_type;
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/*
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* false: for sctl in DUAL_LM_DUAL_DISPLAY
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* true: everything else
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*/
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bool is_master;
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u32 opmode;
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u32 flush_bits;
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u32 flush_reg_data;
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bool split_flush_en;
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bool is_video_mode;
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u32 play_cnt;
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u32 vsync_cnt;
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u32 underrun_cnt;
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u16 width;
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u16 height;
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u16 border_x_off;
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u16 border_y_off;
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bool is_secure;
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/* used for WFD */
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u32 dst_format;
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struct mult_factor dst_comp_ratio;
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u32 clk_rate;
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int force_screen_state;
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struct mdss_mdp_perf_params cur_perf;
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struct mdss_mdp_perf_params new_perf;
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u32 perf_transaction_status;
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bool perf_release_ctl_bw;
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u64 bw_pending;
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bool disable_prefill;
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bool traffic_shaper_enabled;
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u32 traffic_shaper_mdp_clk;
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struct mdss_data_type *mdata;
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struct msm_fb_data_type *mfd;
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struct mdss_mdp_mixer *mixer_left;
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struct mdss_mdp_mixer *mixer_right;
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struct mdss_mdp_cdm *cdm;
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struct mutex lock;
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struct mutex offlock;
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struct mutex flush_lock;
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struct mutex *shared_lock;
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struct mutex rsrc_lock;
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spinlock_t spin_lock;
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struct mdss_panel_data *panel_data;
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struct mdss_mdp_vsync_handler vsync_handler;
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struct mdss_mdp_vsync_handler recover_underrun_handler;
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struct work_struct recover_work;
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struct work_struct remove_underrun_handler;
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/*
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* This ROI is aligned to as per following guidelines and
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* sent to the panel driver.
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*
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* 1. DUAL_LM_DUAL_DISPLAY
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* Panel = 1440x2560
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* CTL0 = 720x2560 (LM0=720x2560)
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* CTL1 = 720x2560 (LM1=720x2560)
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* Both CTL's ROI will be (0-719)x(0-2599)
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* 2. DUAL_LM_SINGLE_DISPLAY
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* Panel = 1440x2560
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* CTL0 = 1440x2560 (LM0=720x2560 and LM1=720x2560)
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* CTL0's ROI will be (0-1429)x(0-2599)
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* 3. SINGLE_LM_SINGLE_DISPLAY
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* Panel = 1080x1920
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* CTL0 = 1080x1920 (LM0=1080x1920)
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* CTL0's ROI will be (0-1079)x(0-1919)
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*/
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struct mdss_rect roi;
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struct mdss_rect roi_bkup;
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struct blocking_notifier_head notifier_head;
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void *priv_data;
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void *intf_ctx[2];
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u32 wb_type;
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struct mdss_mdp_writeback *wb;
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struct mdss_mdp_ctl_intfs_ops ops;
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bool force_ctl_start;
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u64 last_input_time;
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int pending_mode_switch;
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int mixer_cfg_changed;
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};
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struct mdss_mdp_mixer {
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u32 num;
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u32 ref_cnt;
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char __iomem *base;
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char __iomem *dspp_base;
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char __iomem *pingpong_base;
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u8 type;
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u8 params_changed;
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u16 width;
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u16 height;
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bool valid_roi;
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bool roi_changed;
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struct mdss_rect roi;
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u8 cursor_enabled;
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u16 cursor_hotx;
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u16 cursor_hoty;
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u8 rotator_mode;
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/*
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* src_split_req is valid only for right layer mixer.
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*
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* VIDEO mode panels: Always true if source split is enabled.
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* CMD mode panels: Only true if source split is enabled and
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* for a given commit left and right both ROIs
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* are valid.
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*/
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bool src_split_req;
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bool is_right_mixer;
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struct mdss_mdp_ctl *ctl;
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struct mdss_mdp_pipe *stage_pipe[MAX_PIPES_PER_LM];
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u32 next_pipe_map;
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u32 pipe_mapped;
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};
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struct mdss_mdp_format_params {
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u32 format;
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u32 flag;
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u8 is_yuv;
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u8 frame_format;
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u8 chroma_sample;
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u8 solid_fill;
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u8 fetch_planes;
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u8 unpack_align_msb; /* 0 to LSB, 1 to MSB */
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u8 unpack_tight; /* 0 for loose, 1 for tight */
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u8 unpack_count; /* 0 = 1 component, 1 = 2 component ... */
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u8 bpp;
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u8 alpha_enable; /* source has alpha */
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u8 fetch_mode;
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u8 bits[MAX_PLANES];
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u8 element[MAX_PLANES];
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};
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struct mdss_mdp_format_ubwc_tile_info {
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u16 tile_height;
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u16 tile_width;
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};
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struct mdss_mdp_format_params_ubwc {
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struct mdss_mdp_format_params mdp_format;
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struct mdss_mdp_format_ubwc_tile_info micro;
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};
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struct mdss_mdp_plane_sizes {
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u32 num_planes;
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u32 plane_size[MAX_PLANES];
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u32 total_size;
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u32 ystride[MAX_PLANES];
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u32 rau_cnt;
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u32 rau_h[2];
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};
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struct mdss_mdp_img_data {
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dma_addr_t addr;
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unsigned long len;
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u32 offset;
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u32 flags;
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u32 dir;
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bool rotator_smmu;
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bool mapped;
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bool skip_detach;
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struct fd srcp_f;
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struct dma_buf *srcp_dma_buf;
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struct dma_buf_attachment *srcp_attachment;
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struct sg_table *srcp_table;
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};
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enum mdss_mdp_data_state {
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MDP_BUF_STATE_UNUSED,
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MDP_BUF_STATE_READY,
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MDP_BUF_STATE_ACTIVE,
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MDP_BUF_STATE_CLEANUP,
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};
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struct mdss_mdp_data {
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enum mdss_mdp_data_state state;
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u8 num_planes;
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struct mdss_mdp_img_data p[MAX_PLANES];
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struct list_head buf_list;
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struct list_head pipe_list;
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struct list_head chunk_list;
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u64 last_alloc;
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u64 last_freed;
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struct mdss_mdp_pipe *last_pipe;
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};
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struct pp_hist_col_info {
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u32 col_state;
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u32 col_en;
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u32 hist_cnt_read;
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u32 hist_cnt_sent;
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u32 hist_cnt_time;
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u32 frame_cnt;
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u32 data[HIST_V_SIZE];
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struct mutex hist_mutex;
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spinlock_t hist_lock;
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char __iomem *base;
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u32 intr_shift;
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u32 disp_num;
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struct mdss_mdp_ctl *ctl;
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};
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struct mdss_mdp_ad {
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char __iomem *base;
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u8 num;
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};
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struct mdss_ad_info {
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u8 num;
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u8 calc_hw_num;
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|
u32 ops;
|
|
u32 sts;
|
|
u32 reg_sts;
|
|
u32 state;
|
|
u32 ad_data;
|
|
u32 ad_data_mode;
|
|
struct mdss_ad_init init;
|
|
struct mdss_ad_cfg cfg;
|
|
struct mutex lock;
|
|
struct work_struct calc_work;
|
|
struct msm_fb_data_type *mfd;
|
|
struct msm_fb_data_type *bl_mfd;
|
|
struct mdss_mdp_vsync_handler handle;
|
|
u32 last_str;
|
|
u32 last_bl;
|
|
u32 bl_data;
|
|
u32 calc_itr;
|
|
uint32_t bl_lin[AD_BL_LIN_LEN];
|
|
uint32_t bl_lin_inv[AD_BL_LIN_LEN];
|
|
uint32_t bl_att_lut[AD_BL_ATT_LUT_LEN];
|
|
};
|
|
|
|
struct pp_sts_type {
|
|
u32 pa_sts;
|
|
u32 pcc_sts;
|
|
u32 igc_sts;
|
|
u32 igc_tbl_idx;
|
|
u32 argc_sts;
|
|
u32 enhist_sts;
|
|
u32 dither_sts;
|
|
u32 gamut_sts;
|
|
u32 pgc_sts;
|
|
u32 sharp_sts;
|
|
u32 side_sts;
|
|
};
|
|
|
|
struct mdss_pipe_pp_res {
|
|
u32 igc_c0_c1[IGC_LUT_ENTRIES];
|
|
u32 igc_c2[IGC_LUT_ENTRIES];
|
|
u32 hist_lut[ENHIST_LUT_ENTRIES];
|
|
struct pp_hist_col_info hist;
|
|
struct pp_sts_type pp_sts;
|
|
void *pa_cfg_payload;
|
|
void *pcc_cfg_payload;
|
|
void *igc_cfg_payload;
|
|
void *hist_lut_cfg_payload;
|
|
};
|
|
|
|
struct mdss_mdp_pipe_smp_map {
|
|
DECLARE_BITMAP(reserved, MAX_DRV_SUP_MMB_BLKS);
|
|
DECLARE_BITMAP(allocated, MAX_DRV_SUP_MMB_BLKS);
|
|
DECLARE_BITMAP(fixed, MAX_DRV_SUP_MMB_BLKS);
|
|
};
|
|
|
|
struct mdss_mdp_shared_reg_ctrl {
|
|
u32 reg_off;
|
|
u32 bit_off;
|
|
};
|
|
|
|
struct mdss_mdp_pipe {
|
|
u32 num;
|
|
u32 type;
|
|
u32 ndx;
|
|
u8 priority;
|
|
char __iomem *base;
|
|
u32 ftch_id;
|
|
u32 xin_id;
|
|
u32 panic_ctrl_ndx;
|
|
struct mdss_mdp_shared_reg_ctrl clk_ctrl;
|
|
struct mdss_mdp_shared_reg_ctrl clk_status;
|
|
struct mdss_mdp_shared_reg_ctrl sw_reset;
|
|
|
|
struct kref kref;
|
|
|
|
u32 play_cnt;
|
|
struct file *file;
|
|
bool is_handed_off;
|
|
|
|
u32 flags;
|
|
u32 bwc_mode;
|
|
|
|
/* valid only when pipe's output is crossing both layer mixers */
|
|
bool src_split_req;
|
|
bool is_right_blend;
|
|
|
|
u16 img_width;
|
|
u16 img_height;
|
|
u8 horz_deci;
|
|
u8 vert_deci;
|
|
struct mdss_rect src;
|
|
struct mdss_rect dst;
|
|
struct mdss_mdp_format_params *src_fmt;
|
|
struct mdss_mdp_plane_sizes src_planes;
|
|
|
|
/* compression ratio from the source format */
|
|
struct mult_factor comp_ratio;
|
|
|
|
enum mdss_mdp_stage_index mixer_stage;
|
|
u8 is_fg;
|
|
u8 alpha;
|
|
u8 blend_op;
|
|
u8 overfetch_disable;
|
|
u32 transp;
|
|
u32 bg_color;
|
|
|
|
struct msm_fb_data_type *mfd;
|
|
struct mdss_mdp_mixer *mixer_left;
|
|
struct mdss_mdp_mixer *mixer_right;
|
|
|
|
struct mdp_overlay req_data;
|
|
struct mdp_input_layer layer;
|
|
u32 params_changed;
|
|
bool dirty;
|
|
bool unhalted;
|
|
bool async_update;
|
|
|
|
struct mdss_mdp_pipe_smp_map smp_map[MAX_PLANES];
|
|
|
|
struct list_head buf_queue;
|
|
struct list_head list;
|
|
|
|
struct mdp_overlay_pp_params pp_cfg;
|
|
struct mdss_pipe_pp_res pp_res;
|
|
struct mdp_scale_data scale;
|
|
u8 chroma_sample_h;
|
|
u8 chroma_sample_v;
|
|
|
|
wait_queue_head_t free_waitq;
|
|
u32 frame_rate;
|
|
enum mdp_color_space csc_coeff_set;
|
|
};
|
|
|
|
struct mdss_mdp_writeback_arg {
|
|
struct mdss_mdp_data *data;
|
|
void *priv_data;
|
|
};
|
|
|
|
struct mdss_mdp_wfd;
|
|
|
|
struct mdss_overlay_private {
|
|
ktime_t vsync_time;
|
|
struct kernfs_node *vsync_event_sd;
|
|
struct kernfs_node *hist_event_sd;
|
|
struct kernfs_node *bl_event_sd;
|
|
struct kernfs_node *ad_event_sd;
|
|
struct kernfs_node *ad_bl_event_sd;
|
|
int borderfill_enable;
|
|
int hw_refresh;
|
|
void *cpu_pm_hdl;
|
|
|
|
struct mdss_data_type *mdata;
|
|
struct mutex ov_lock;
|
|
struct mutex dfps_lock;
|
|
struct mdss_mdp_ctl *ctl;
|
|
struct mdss_mdp_wfd *wfd;
|
|
|
|
struct mutex list_lock;
|
|
struct list_head pipes_used;
|
|
struct list_head pipes_cleanup;
|
|
struct list_head pipes_destroy;
|
|
struct list_head rot_proc_list;
|
|
bool mixer_swap;
|
|
u32 resources_state;
|
|
|
|
/* list of buffers that can be reused */
|
|
struct list_head bufs_chunks;
|
|
struct list_head bufs_pool;
|
|
struct list_head bufs_used;
|
|
/* list of buffers which should be freed during cleanup stage */
|
|
struct list_head bufs_freelist;
|
|
|
|
int ad_state;
|
|
int dyn_pu_state;
|
|
|
|
bool handoff;
|
|
u32 splash_mem_addr;
|
|
u32 splash_mem_size;
|
|
u32 sd_enabled;
|
|
|
|
struct sw_sync_timeline *vsync_timeline;
|
|
struct mdss_mdp_vsync_handler vsync_retire_handler;
|
|
struct work_struct retire_work;
|
|
int retire_cnt;
|
|
bool kickoff_released;
|
|
u32 cursor_ndx[2];
|
|
u32 hist_events;
|
|
u32 bl_events;
|
|
u32 ad_events;
|
|
u32 ad_bl_events;
|
|
};
|
|
|
|
struct mdss_mdp_set_ot_params {
|
|
u32 xin_id;
|
|
u32 num;
|
|
u32 width;
|
|
u32 height;
|
|
bool is_rot;
|
|
bool is_wb;
|
|
bool is_yuv;
|
|
bool is_vbif_nrt;
|
|
u32 reg_off_vbif_lim_conf;
|
|
u32 reg_off_mdp_clk_ctrl;
|
|
u32 bit_off_mdp_clk_ctrl;
|
|
};
|
|
|
|
struct mdss_mdp_commit_cb {
|
|
void *data;
|
|
int (*commit_cb_fnc) (enum mdp_commit_stage_type commit_state,
|
|
void *data);
|
|
};
|
|
|
|
/**
|
|
* enum mdss_screen_state - Screen states that MDP can be forced into
|
|
*
|
|
* @MDSS_SCREEN_DEFAULT: Do not force MDP into any screen state.
|
|
* @MDSS_SCREEN_FORCE_BLANK: Force MDP to generate blank color fill screen.
|
|
*/
|
|
enum mdss_screen_state {
|
|
MDSS_SCREEN_DEFAULT,
|
|
MDSS_SCREEN_FORCE_BLANK,
|
|
};
|
|
|
|
/**
|
|
* enum mdss_mdp_clt_intf_event_flags - flags specifying how event to should
|
|
* be sent to panel drivers.
|
|
*
|
|
* @CTL_INTF_EVENT_FLAG_DEFAULT: this flag denotes default behaviour where
|
|
* event will be send to all panels attached this
|
|
* display, recursively in split-DSI.
|
|
* @CTL_INTF_EVENT_FLAG_SKIP_BROADCAST: this flag sends event only to panel
|
|
* associated with this ctl.
|
|
* @CTL_INTF_EVENT_FLAG_SLAVE_INTF: this flag sends event only to slave panel
|
|
* associated with this ctl, i.e pingpong-split
|
|
*/
|
|
enum mdss_mdp_clt_intf_event_flags {
|
|
CTL_INTF_EVENT_FLAG_DEFAULT = 0,
|
|
CTL_INTF_EVENT_FLAG_SKIP_BROADCAST = BIT(1),
|
|
CTL_INTF_EVENT_FLAG_SLAVE_INTF = BIT(2),
|
|
};
|
|
|
|
#define mfd_to_mdp5_data(mfd) (mfd->mdp.private1)
|
|
#define mfd_to_mdata(mfd) (((struct mdss_overlay_private *)\
|
|
(mfd->mdp.private1))->mdata)
|
|
#define mfd_to_ctl(mfd) (((struct mdss_overlay_private *)\
|
|
(mfd->mdp.private1))->ctl)
|
|
#define mfd_to_wb(mfd) (((struct mdss_overlay_private *)\
|
|
(mfd->mdp.private1))->wb)
|
|
|
|
/**
|
|
* - mdss_mdp_is_roi_changed
|
|
* @mfd - pointer to mfd
|
|
*
|
|
* Function returns true if roi is changed for any layer mixer of a given
|
|
* display, false otherwise.
|
|
*/
|
|
static inline bool mdss_mdp_is_roi_changed(struct msm_fb_data_type *mfd)
|
|
{
|
|
struct mdss_mdp_ctl *ctl;
|
|
|
|
if (!mfd)
|
|
return false;
|
|
|
|
ctl = mfd_to_ctl(mfd); /* returns master ctl */
|
|
|
|
return ctl->mixer_left->roi_changed ||
|
|
(is_split_lm(mfd) ? ctl->mixer_right->roi_changed : false);
|
|
}
|
|
|
|
/**
|
|
* - mdss_mdp_is_both_lm_valid
|
|
* @main_ctl - pointer to a main ctl
|
|
*
|
|
* Function checks if both layer mixers are active or not. This can be useful
|
|
* when partial update is enabled on either MDP_DUAL_LM_SINGLE_DISPLAY or
|
|
* MDP_DUAL_LM_DUAL_DISPLAY .
|
|
*/
|
|
static inline bool mdss_mdp_is_both_lm_valid(struct mdss_mdp_ctl *main_ctl)
|
|
{
|
|
return (main_ctl && main_ctl->is_master &&
|
|
main_ctl->mixer_left && main_ctl->mixer_left->valid_roi &&
|
|
main_ctl->mixer_right && main_ctl->mixer_right->valid_roi);
|
|
}
|
|
|
|
static inline struct mdss_mdp_ctl *mdss_mdp_get_split_ctl(
|
|
struct mdss_mdp_ctl *ctl)
|
|
{
|
|
if (ctl && ctl->mixer_right && (ctl->mixer_right->ctl != ctl))
|
|
return ctl->mixer_right->ctl;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static inline struct mdss_mdp_ctl *mdss_mdp_get_main_ctl(
|
|
struct mdss_mdp_ctl *sctl)
|
|
{
|
|
if (sctl && sctl->mfd && sctl->mixer_left &&
|
|
sctl->mixer_left->is_right_mixer)
|
|
return mfd_to_ctl(sctl->mfd);
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static inline bool mdss_mdp_pipe_is_yuv(struct mdss_mdp_pipe *pipe)
|
|
{
|
|
return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_VIG);
|
|
}
|
|
|
|
static inline bool mdss_mdp_pipe_is_rgb(struct mdss_mdp_pipe *pipe)
|
|
{
|
|
return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_RGB);
|
|
}
|
|
|
|
static inline bool mdss_mdp_pipe_is_dma(struct mdss_mdp_pipe *pipe)
|
|
{
|
|
return pipe && (pipe->type == MDSS_MDP_PIPE_TYPE_DMA);
|
|
}
|
|
|
|
static inline void mdss_mdp_ctl_write(struct mdss_mdp_ctl *ctl,
|
|
u32 reg, u32 val)
|
|
{
|
|
writel_relaxed(val, ctl->base + reg);
|
|
}
|
|
|
|
static inline u32 mdss_mdp_ctl_read(struct mdss_mdp_ctl *ctl, u32 reg)
|
|
{
|
|
return readl_relaxed(ctl->base + reg);
|
|
}
|
|
|
|
static inline void mdp_mixer_write(struct mdss_mdp_mixer *mixer,
|
|
u32 reg, u32 val)
|
|
{
|
|
writel_relaxed(val, mixer->base + reg);
|
|
}
|
|
|
|
static inline u32 mdp_mixer_read(struct mdss_mdp_mixer *mixer, u32 reg)
|
|
{
|
|
return readl_relaxed(mixer->base + reg);
|
|
}
|
|
|
|
static inline void mdss_mdp_pingpong_write(char __iomem *pingpong_base,
|
|
u32 reg, u32 val)
|
|
{
|
|
writel_relaxed(val, pingpong_base + reg);
|
|
}
|
|
|
|
static inline u32 mdss_mdp_pingpong_read(char __iomem *pingpong_base, u32 reg)
|
|
{
|
|
return readl_relaxed(pingpong_base + reg);
|
|
}
|
|
|
|
static inline int mdss_mdp_pipe_is_sw_reset_available(
|
|
struct mdss_data_type *mdata)
|
|
{
|
|
switch (mdata->mdp_rev) {
|
|
case MDSS_MDP_HW_REV_101_2:
|
|
case MDSS_MDP_HW_REV_103_1:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static inline int mdss_mdp_iommu_dyn_attach_supported(
|
|
struct mdss_data_type *mdata)
|
|
{
|
|
return (mdata->mdp_rev >= MDSS_MDP_HW_REV_103);
|
|
}
|
|
|
|
static inline int mdss_mdp_line_buffer_width(void)
|
|
{
|
|
return MAX_LINE_BUFFER_WIDTH;
|
|
}
|
|
|
|
static inline u32 get_panel_yres(struct mdss_panel_info *pinfo)
|
|
{
|
|
u32 yres;
|
|
|
|
yres = pinfo->yres + pinfo->lcdc.border_top +
|
|
pinfo->lcdc.border_bottom;
|
|
return yres;
|
|
}
|
|
|
|
static inline u32 get_panel_xres(struct mdss_panel_info *pinfo)
|
|
{
|
|
u32 xres;
|
|
|
|
xres = pinfo->xres + pinfo->lcdc.border_left +
|
|
pinfo->lcdc.border_right;
|
|
return xres;
|
|
}
|
|
|
|
static inline u32 get_panel_width(struct mdss_mdp_ctl *ctl)
|
|
{
|
|
u32 width;
|
|
|
|
width = get_panel_xres(&ctl->panel_data->panel_info);
|
|
if (ctl->panel_data->next && is_pingpong_split(ctl->mfd))
|
|
width += get_panel_xres(&ctl->panel_data->next->panel_info);
|
|
|
|
return width;
|
|
}
|
|
|
|
static inline int mdss_mdp_panic_signal_support_mode(
|
|
struct mdss_data_type *mdata)
|
|
{
|
|
uint32_t signal_mode = MDSS_MDP_PANIC_NONE;
|
|
|
|
if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,
|
|
MDSS_MDP_HW_REV_105) ||
|
|
IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,
|
|
MDSS_MDP_HW_REV_108) ||
|
|
IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,
|
|
MDSS_MDP_HW_REV_109) ||
|
|
IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,
|
|
MDSS_MDP_HW_REV_110))
|
|
signal_mode = MDSS_MDP_PANIC_COMMON_REG_CFG;
|
|
else if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev,
|
|
MDSS_MDP_HW_REV_107))
|
|
signal_mode = MDSS_MDP_PANIC_PER_PIPE_CFG;
|
|
|
|
return signal_mode;
|
|
}
|
|
|
|
static inline struct clk *mdss_mdp_get_clk(u32 clk_idx)
|
|
{
|
|
if (clk_idx < MDSS_MAX_CLK)
|
|
return mdss_res->mdp_clk[clk_idx];
|
|
return NULL;
|
|
}
|
|
|
|
static inline void mdss_update_sd_client(struct mdss_data_type *mdata,
|
|
bool status)
|
|
{
|
|
if (status)
|
|
atomic_inc(&mdata->sd_client_count);
|
|
else
|
|
atomic_add_unless(&mdss_res->sd_client_count, -1, 0);
|
|
}
|
|
|
|
static inline int mdss_mdp_get_wb_ctl_support(struct mdss_data_type *mdata,
|
|
bool rotator_session)
|
|
{
|
|
/*
|
|
* Initial control paths are used for primary and external
|
|
* interfaces and remaining control paths are used for WB
|
|
* interfaces.
|
|
*/
|
|
return rotator_session ? (mdata->nctl - mdata->nmixers_wb) :
|
|
(mdata->nctl - mdata->nwb);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_nrt_vbif_client(struct mdss_data_type *mdata,
|
|
struct mdss_mdp_pipe *pipe)
|
|
{
|
|
return mdata->vbif_nrt_io.base && pipe->mixer_left &&
|
|
pipe->mixer_left->rotator_mode;
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_nrt_ctl_path(struct mdss_mdp_ctl *ctl)
|
|
{
|
|
return (ctl->intf_num == MDSS_MDP_NO_INTF) ||
|
|
(ctl->mixer_left && ctl->mixer_left->rotator_mode);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_nrt_vbif_base_defined(
|
|
struct mdss_data_type *mdata)
|
|
{
|
|
return mdata->vbif_nrt_io.base ? true : false;
|
|
}
|
|
|
|
static inline bool mdss_mdp_ctl_is_power_off(struct mdss_mdp_ctl *ctl)
|
|
{
|
|
return mdss_panel_is_power_off(ctl->power_state);
|
|
}
|
|
|
|
static inline bool mdss_mdp_ctl_is_power_on_interactive(
|
|
struct mdss_mdp_ctl *ctl)
|
|
{
|
|
return mdss_panel_is_power_on_interactive(ctl->power_state);
|
|
}
|
|
|
|
static inline bool mdss_mdp_ctl_is_power_on(struct mdss_mdp_ctl *ctl)
|
|
{
|
|
return mdss_panel_is_power_on(ctl->power_state);
|
|
}
|
|
|
|
static inline bool mdss_mdp_ctl_is_power_on_lp(struct mdss_mdp_ctl *ctl)
|
|
{
|
|
return mdss_panel_is_power_on_lp(ctl->power_state);
|
|
}
|
|
|
|
static inline u32 left_lm_w_from_mfd(struct msm_fb_data_type *mfd)
|
|
{
|
|
struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd);
|
|
struct mdss_panel_info *pinfo = mfd->panel_info;
|
|
int width = 0;
|
|
|
|
if (ctl && ctl->mixer_left) {
|
|
width = ctl->mixer_left->width;
|
|
width -= (pinfo->lcdc.border_left + pinfo->lcdc.border_right);
|
|
pr_debug("ctl=%d mw=%d l=%d r=%d w=%d\n",
|
|
ctl->num, ctl->mixer_left->width,
|
|
pinfo->lcdc.border_left, pinfo->lcdc.border_right,
|
|
width);
|
|
}
|
|
return width;
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_tile_format(struct mdss_mdp_format_params *fmt)
|
|
{
|
|
return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_TILE);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_ubwc_format(struct mdss_mdp_format_params *fmt)
|
|
{
|
|
return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_UBWC);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_linear_format(struct mdss_mdp_format_params *fmt)
|
|
{
|
|
return fmt && (fmt->fetch_mode == MDSS_MDP_FETCH_LINEAR);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_nv12_format(struct mdss_mdp_format_params *fmt)
|
|
{
|
|
return fmt && (fmt->chroma_sample == MDSS_MDP_CHROMA_420) &&
|
|
(fmt->fetch_planes == MDSS_MDP_PLANE_PSEUDO_PLANAR);
|
|
}
|
|
|
|
static inline bool mdss_mdp_is_ubwc_supported(struct mdss_data_type *mdata)
|
|
{
|
|
return mdata->has_ubwc;
|
|
}
|
|
|
|
static inline int mdss_mdp_is_cdm_supported(struct mdss_data_type *mdata,
|
|
u32 intf_type, u32 mixer_type)
|
|
{
|
|
int support = mdata->ncdm;
|
|
|
|
/*
|
|
* CDM is supported under these conditions
|
|
* 1. If Device tree created a cdm block AND
|
|
* 2. Output interface is HDMI OR Output interface is WB2
|
|
*/
|
|
return support && ((intf_type == MDSS_INTF_HDMI) ||
|
|
((intf_type == MDSS_MDP_NO_INTF) &&
|
|
(mixer_type == MDSS_MDP_MIXER_TYPE_INTF)));
|
|
}
|
|
|
|
static inline u32 mdss_mdp_get_cursor_frame_size(struct mdss_data_type *mdata)
|
|
{
|
|
return mdata->max_cursor_size * mdata->max_cursor_size * 4;
|
|
}
|
|
|
|
static inline uint8_t pp_vig_csc_pipe_val(struct mdss_mdp_pipe *pipe)
|
|
{
|
|
switch (pipe->csc_coeff_set) {
|
|
case MDP_CSC_ITU_R_601:
|
|
return MDSS_MDP_CSC_YUV2RGB_601L;
|
|
case MDP_CSC_ITU_R_601_FR:
|
|
return MDSS_MDP_CSC_YUV2RGB_601FR;
|
|
case MDP_CSC_ITU_R_2020:
|
|
return MDSS_MDP_CSC_YUV2RGB_2020L;
|
|
case MDP_CSC_ITU_R_2020_FR:
|
|
return MDSS_MDP_CSC_YUV2RGB_2020FR;
|
|
case MDP_CSC_ITU_R_P3:
|
|
return MDSS_MDP_CSC_YUV2RGB_P3L;
|
|
case MDP_CSC_ITU_R_P3_FR:
|
|
return MDSS_MDP_CSC_YUV2RGB_P3FR;
|
|
case MDP_CSC_ITU_R_709:
|
|
default:
|
|
return MDSS_MDP_CSC_YUV2RGB_709L;
|
|
}
|
|
}
|
|
/*
|
|
* when DUAL_LM_SINGLE_DISPLAY is used with 2 DSC encoders, DSC_MERGE is
|
|
* used during full frame updates. Now when we go from full frame update
|
|
* to right-only update, we need to disable DSC_MERGE. However, DSC_MERGE
|
|
* is controlled through DSC0_COMMON_MODE register which is double buffered,
|
|
* and this double buffer update is tied to LM0. Now for right-only update,
|
|
* LM0 will not get double buffer update signal. So DSC_MERGE is not disabled
|
|
* for right-only update which is wrong HW state and leads ping-pong timeout.
|
|
* Workaround for this is to use LM0->DSC0 pair for right-only update
|
|
* and disable DSC_MERGE.
|
|
*
|
|
* However using LM0->DSC0 pair for right-only update requires many changes
|
|
* at various levels of SW. To lower the SW impact and still support
|
|
* right-only partial update, keep SW state as it is but swap mixer register
|
|
* writes such that we instruct HW to use LM0->DSC0 pair.
|
|
*
|
|
* This function will return true if such a swap is needed or not.
|
|
*/
|
|
static inline bool mdss_mdp_is_lm_swap_needed(struct mdss_data_type *mdata,
|
|
struct mdss_mdp_ctl *mctl)
|
|
{
|
|
if (!mdata || !mctl || !mctl->is_master ||
|
|
!mctl->panel_data || !mctl->mfd)
|
|
return false;
|
|
|
|
return (is_dual_lm_single_display(mctl->mfd)) &&
|
|
(mctl->panel_data->panel_info.partial_update_enabled) &&
|
|
(mdss_has_quirk(mdata, MDSS_QUIRK_DSC_RIGHT_ONLY_PU)) &&
|
|
(is_dsc_compression(&mctl->panel_data->panel_info)) &&
|
|
(mctl->panel_data->panel_info.dsc_enc_total == 2) &&
|
|
(!mctl->mixer_left->valid_roi) &&
|
|
(mctl->mixer_right->valid_roi);
|
|
}
|
|
|
|
irqreturn_t mdss_mdp_isr(int irq, void *ptr);
|
|
void mdss_mdp_irq_clear(struct mdss_data_type *mdata,
|
|
u32 intr_type, u32 intf_num);
|
|
int mdss_mdp_irq_enable(u32 intr_type, u32 intf_num);
|
|
void mdss_mdp_irq_disable(u32 intr_type, u32 intf_num);
|
|
void mdss_mdp_intr_check_and_clear(u32 intr_type, u32 intf_num);
|
|
int mdss_mdp_hist_irq_enable(u32 irq);
|
|
void mdss_mdp_hist_irq_disable(u32 irq);
|
|
void mdss_mdp_irq_disable_nosync(u32 intr_type, u32 intf_num);
|
|
int mdss_mdp_set_intr_callback(u32 intr_type, u32 intf_num,
|
|
void (*fnc_ptr)(void *), void *arg);
|
|
int mdss_mdp_set_intr_callback_nosync(u32 intr_type, u32 intf_num,
|
|
void (*fnc_ptr)(void *), void *arg);
|
|
|
|
void mdss_mdp_footswitch_ctrl_splash(int on);
|
|
void mdss_mdp_batfet_ctrl(struct mdss_data_type *mdata, int enable);
|
|
void mdss_mdp_set_clk_rate(unsigned long min_clk_rate);
|
|
unsigned long mdss_mdp_get_clk_rate(u32 clk_idx, bool locked);
|
|
int mdss_mdp_vsync_clk_enable(int enable, bool locked);
|
|
void mdss_mdp_clk_ctrl(int enable);
|
|
struct mdss_data_type *mdss_mdp_get_mdata(void);
|
|
int mdss_mdp_secure_display_ctrl(unsigned int enable);
|
|
|
|
int mdss_mdp_overlay_init(struct msm_fb_data_type *mfd);
|
|
int mdss_mdp_layer_atomic_validate(struct msm_fb_data_type *mfd,
|
|
struct file *file, struct mdp_layer_commit_v1 *ov_commit);
|
|
int mdss_mdp_layer_pre_commit(struct msm_fb_data_type *mfd,
|
|
struct file *file, struct mdp_layer_commit_v1 *ov_commit);
|
|
|
|
int mdss_mdp_layer_atomic_validate_wfd(struct msm_fb_data_type *mfd,
|
|
struct file *file, struct mdp_layer_commit_v1 *ov_commit);
|
|
int mdss_mdp_layer_pre_commit_wfd(struct msm_fb_data_type *mfd,
|
|
struct file *file, struct mdp_layer_commit_v1 *ov_commit);
|
|
|
|
int mdss_mdp_async_position_update(struct msm_fb_data_type *mfd,
|
|
struct mdp_position_update *update_pos);
|
|
|
|
int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd,
|
|
struct mdp_overlay *req,
|
|
struct mdss_mdp_format_params *fmt);
|
|
int mdss_mdp_overlay_vsync_ctrl(struct msm_fb_data_type *mfd, int en);
|
|
int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd,
|
|
struct mdp_overlay *req, struct mdss_mdp_pipe **ppipe,
|
|
struct mdss_mdp_pipe *left_blend_pipe, bool is_single_layer);
|
|
void mdss_mdp_handoff_cleanup_pipes(struct msm_fb_data_type *mfd,
|
|
u32 type);
|
|
int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx);
|
|
int mdss_mdp_overlay_start(struct msm_fb_data_type *mfd);
|
|
void mdss_mdp_overlay_set_chroma_sample(
|
|
struct mdss_mdp_pipe *pipe);
|
|
int mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe,
|
|
u32 flags);
|
|
int mdss_mdp_overlay_setup_scaling(struct mdss_mdp_pipe *pipe);
|
|
struct mdss_mdp_pipe *mdss_mdp_pipe_assign(struct mdss_data_type *mdata,
|
|
struct mdss_mdp_mixer *mixer, u32 ndx);
|
|
struct mdss_mdp_pipe *mdss_mdp_overlay_pipe_reuse(
|
|
struct msm_fb_data_type *mfd, int pipe_ndx);
|
|
void mdss_mdp_pipe_position_update(struct mdss_mdp_pipe *pipe,
|
|
struct mdss_rect *src, struct mdss_rect *dst);
|
|
int mdss_mdp_video_addr_setup(struct mdss_data_type *mdata,
|
|
u32 *offsets, u32 count);
|
|
int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl);
|
|
void mdss_mdp_switch_roi_reset(struct mdss_mdp_ctl *ctl);
|
|
void mdss_mdp_switch_to_cmd_mode(struct mdss_mdp_ctl *ctl, int prep);
|
|
void mdss_mdp_switch_to_vid_mode(struct mdss_mdp_ctl *ctl, int prep);
|
|
void *mdss_mdp_get_intf_base_addr(struct mdss_data_type *mdata,
|
|
u32 interface_id);
|
|
int mdss_mdp_cmd_start(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_writeback_start(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd,
|
|
struct mdp_display_commit *data);
|
|
struct mdss_mdp_data *mdss_mdp_overlay_buf_alloc(struct msm_fb_data_type *mfd,
|
|
struct mdss_mdp_pipe *pipe);
|
|
void mdss_mdp_overlay_buf_free(struct msm_fb_data_type *mfd,
|
|
struct mdss_mdp_data *buf);
|
|
|
|
int mdss_mdp_ctl_reconfig(struct mdss_mdp_ctl *ctl,
|
|
struct mdss_panel_data *pdata);
|
|
struct mdss_mdp_ctl *mdss_mdp_ctl_init(struct mdss_panel_data *pdata,
|
|
struct msm_fb_data_type *mfd);
|
|
int mdss_mdp_video_reconfigure_splash_done(struct mdss_mdp_ctl *ctl,
|
|
bool handoff);
|
|
int mdss_mdp_cmd_reconfigure_splash_done(struct mdss_mdp_ctl *ctl,
|
|
bool handoff);
|
|
int mdss_mdp_ctl_splash_finish(struct mdss_mdp_ctl *ctl, bool handoff);
|
|
int mdss_mdp_ctl_setup(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_ctl_split_display_setup(struct mdss_mdp_ctl *ctl,
|
|
struct mdss_panel_data *pdata);
|
|
int mdss_mdp_ctl_destroy(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_ctl_start(struct mdss_mdp_ctl *ctl, bool handoff);
|
|
int mdss_mdp_ctl_stop(struct mdss_mdp_ctl *ctl, int panel_power_mode);
|
|
int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg,
|
|
u32 flags);
|
|
int mdss_mdp_get_prefetch_lines(struct mdss_panel_info *pinfo);
|
|
int mdss_mdp_perf_bw_check(struct mdss_mdp_ctl *ctl,
|
|
struct mdss_mdp_pipe **left_plist, int left_cnt,
|
|
struct mdss_mdp_pipe **right_plist, int right_cnt);
|
|
int mdss_mdp_perf_bw_check_pipe(struct mdss_mdp_perf_params *perf,
|
|
struct mdss_mdp_pipe *pipe);
|
|
int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe,
|
|
struct mdss_mdp_perf_params *perf, struct mdss_rect *roi,
|
|
u32 flags);
|
|
u32 mdss_mdp_calc_latency_buf_bytes(bool is_yuv, bool is_bwc,
|
|
bool is_tile, u32 src_w, u32 bpp, bool use_latency_buf_percentage,
|
|
u32 smp_bytes, bool is_ubwc, bool is_nv12, bool is_hflip);
|
|
u32 mdss_mdp_get_mdp_clk_rate(struct mdss_data_type *mdata);
|
|
int mdss_mdp_ctl_notify(struct mdss_mdp_ctl *ctl, int event);
|
|
void mdss_mdp_ctl_notifier_register(struct mdss_mdp_ctl *ctl,
|
|
struct notifier_block *notifier);
|
|
void mdss_mdp_ctl_notifier_unregister(struct mdss_mdp_ctl *ctl,
|
|
struct notifier_block *notifier);
|
|
u32 mdss_mdp_ctl_perf_get_transaction_status(struct mdss_mdp_ctl *ctl);
|
|
u32 apply_comp_ratio_factor(u32 quota, struct mdss_mdp_format_params *fmt,
|
|
struct mult_factor *factor);
|
|
|
|
int mdss_mdp_scan_pipes(void);
|
|
|
|
int mdss_mdp_mixer_handoff(struct mdss_mdp_ctl *ctl, u32 num,
|
|
struct mdss_mdp_pipe *pipe);
|
|
|
|
void mdss_mdp_ctl_perf_set_transaction_status(struct mdss_mdp_ctl *ctl,
|
|
enum mdss_mdp_perf_state_type component, bool new_status);
|
|
void mdss_mdp_ctl_perf_release_bw(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_async_ctl_flush(struct msm_fb_data_type *mfd,
|
|
u32 flush_bits);
|
|
int mdss_mdp_get_pipe_flush_bits(struct mdss_mdp_pipe *pipe);
|
|
struct mdss_mdp_mixer *mdss_mdp_block_mixer_alloc(void);
|
|
int mdss_mdp_block_mixer_destroy(struct mdss_mdp_mixer *mixer);
|
|
struct mdss_mdp_mixer *mdss_mdp_mixer_get(struct mdss_mdp_ctl *ctl, int mux);
|
|
struct mdss_mdp_pipe *mdss_mdp_get_staged_pipe(struct mdss_mdp_ctl *ctl,
|
|
int mux, int stage, bool is_right_blend);
|
|
int mdss_mdp_mixer_pipe_update(struct mdss_mdp_pipe *pipe,
|
|
struct mdss_mdp_mixer *mixer, int params_changed);
|
|
int mdss_mdp_mixer_pipe_unstage(struct mdss_mdp_pipe *pipe,
|
|
struct mdss_mdp_mixer *mixer);
|
|
void mdss_mdp_mixer_unstage_all(struct mdss_mdp_mixer *mixer);
|
|
int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg,
|
|
struct mdss_mdp_commit_cb *commit_cb);
|
|
int mdss_mdp_display_wait4comp(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_display_wait4pingpong(struct mdss_mdp_ctl *ctl, bool use_lock);
|
|
int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
|
|
ktime_t *wakeup_time);
|
|
|
|
int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 csc_type);
|
|
int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, struct mdp_csc_cfg *data);
|
|
|
|
int mdss_mdp_pp_init(struct device *dev);
|
|
void mdss_mdp_pp_term(struct device *dev);
|
|
int mdss_mdp_pp_overlay_init(struct msm_fb_data_type *mfd);
|
|
|
|
int mdss_mdp_pp_resume(struct msm_fb_data_type *mfd);
|
|
|
|
int mdss_mdp_pp_setup(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl);
|
|
int mdss_mdp_pipe_pp_setup(struct mdss_mdp_pipe *pipe, u32 *op);
|
|
void mdss_mdp_pipe_pp_clear(struct mdss_mdp_pipe *pipe);
|
|
int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op);
|
|
int mdss_mdp_pp_sspp_config(struct mdss_mdp_pipe *pipe);
|
|
int mdss_mdp_copy_layer_pp_info(struct mdp_input_layer *layer);
|
|
void mdss_mdp_free_layer_pp_info(struct mdp_input_layer *layer);
|
|
|
|
int mdss_mdp_smp_setup(struct mdss_data_type *mdata, u32 cnt, u32 size);
|
|
|
|
void mdss_hw_init(struct mdss_data_type *mdata);
|
|
|
|
int mdss_mdp_mfd_valid_dspp(struct msm_fb_data_type *mfd);
|
|
|
|
int mdss_mdp_pa_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_pa_cfg_data *config, u32 *copyback);
|
|
int mdss_mdp_pa_v2_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_pa_v2_cfg_data *config, u32 *copyback);
|
|
int mdss_mdp_pcc_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_pcc_cfg_data *cfg_ptr, u32 *copyback);
|
|
int mdss_mdp_igc_lut_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_igc_lut_data *config, u32 *copyback,
|
|
u32 copy_from_kernel);
|
|
int mdss_mdp_argc_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_pgc_lut_data *config, u32 *copyback);
|
|
int mdss_mdp_hist_lut_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_hist_lut_data *config, u32 *copyback);
|
|
int mdss_mdp_pp_default_overlay_config(struct msm_fb_data_type *mfd,
|
|
struct mdss_panel_data *pdata);
|
|
int mdss_mdp_dither_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_dither_cfg_data *config, u32 *copyback,
|
|
int copy_from_kernel);
|
|
int mdss_mdp_gamut_config(struct msm_fb_data_type *mfd,
|
|
struct mdp_gamut_cfg_data *config, u32 *copyback);
|
|
|
|
int mdss_mdp_hist_intr_req(struct mdss_intr *intr, u32 bits, bool en);
|
|
int mdss_mdp_hist_intr_setup(struct mdss_intr *intr, int state);
|
|
int mdss_mdp_hist_start(struct mdp_histogram_start_req *req);
|
|
int mdss_mdp_hist_stop(u32 block);
|
|
int mdss_mdp_hist_collect(struct mdp_histogram_data *hist);
|
|
void mdss_mdp_hist_intr_done(u32 isr);
|
|
|
|
int mdss_mdp_ad_config(struct msm_fb_data_type *mfd,
|
|
struct mdss_ad_init_cfg *init_cfg);
|
|
int mdss_mdp_ad_input(struct msm_fb_data_type *mfd,
|
|
struct mdss_ad_input *input, int wait);
|
|
int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_offsets);
|
|
int mdss_mdp_calib_mode(struct msm_fb_data_type *mfd,
|
|
struct mdss_calib_cfg *cfg);
|
|
|
|
int mdss_mdp_pipe_handoff(struct mdss_mdp_pipe *pipe);
|
|
int mdss_mdp_smp_handoff(struct mdss_data_type *mdata);
|
|
struct mdss_mdp_pipe *mdss_mdp_pipe_alloc(struct mdss_mdp_mixer *mixer,
|
|
u32 type, struct mdss_mdp_pipe *left_blend_pipe);
|
|
struct mdss_mdp_pipe *mdss_mdp_pipe_get(struct mdss_data_type *mdata, u32 ndx);
|
|
struct mdss_mdp_pipe *mdss_mdp_pipe_search(struct mdss_data_type *mdata,
|
|
u32 ndx);
|
|
int mdss_mdp_pipe_map(struct mdss_mdp_pipe *pipe);
|
|
void mdss_mdp_pipe_unmap(struct mdss_mdp_pipe *pipe);
|
|
struct mdss_mdp_pipe *mdss_mdp_pipe_alloc_dma(struct mdss_mdp_mixer *mixer);
|
|
|
|
u32 mdss_mdp_smp_calc_num_blocks(struct mdss_mdp_pipe *pipe);
|
|
u32 mdss_mdp_smp_get_size(struct mdss_mdp_pipe *pipe);
|
|
int mdss_mdp_smp_reserve(struct mdss_mdp_pipe *pipe);
|
|
void mdss_mdp_smp_unreserve(struct mdss_mdp_pipe *pipe);
|
|
void mdss_mdp_smp_release(struct mdss_mdp_pipe *pipe);
|
|
|
|
int mdss_mdp_pipe_addr_setup(struct mdss_data_type *mdata,
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struct mdss_mdp_pipe *head, u32 *offsets, u32 *ftch_y_id, u32 *xin_id,
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u32 type, u32 num_base, u32 len, u8 priority_base);
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int mdss_mdp_mixer_addr_setup(struct mdss_data_type *mdata, u32 *mixer_offsets,
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u32 *dspp_offsets, u32 *pingpong_offsets, u32 type, u32 len);
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int mdss_mdp_ctl_addr_setup(struct mdss_data_type *mdata, u32 *ctl_offsets,
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u32 len);
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int mdss_mdp_wb_addr_setup(struct mdss_data_type *mdata,
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u32 num_wb, u32 num_intf_wb);
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void mdss_mdp_pipe_clk_force_off(struct mdss_mdp_pipe *pipe);
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int mdss_mdp_pipe_fetch_halt(struct mdss_mdp_pipe *pipe, bool is_recovery);
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int mdss_mdp_pipe_panic_signal_ctrl(struct mdss_mdp_pipe *pipe, bool enable);
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void mdss_mdp_bwcpanic_ctrl(struct mdss_data_type *mdata, bool enable);
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int mdss_mdp_pipe_destroy(struct mdss_mdp_pipe *pipe);
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int mdss_mdp_pipe_queue_data(struct mdss_mdp_pipe *pipe,
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struct mdss_mdp_data *src_data);
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int mdss_mdp_vbif_axi_halt(struct mdss_data_type *mdata);
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int mdss_mdp_data_check(struct mdss_mdp_data *data,
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struct mdss_mdp_plane_sizes *ps,
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struct mdss_mdp_format_params *fmt);
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int mdss_mdp_get_plane_sizes(struct mdss_mdp_format_params *fmt, u32 w, u32 h,
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struct mdss_mdp_plane_sizes *ps, u32 bwc_mode, bool rotation);
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int mdss_mdp_get_rau_strides(u32 w, u32 h, struct mdss_mdp_format_params *fmt,
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struct mdss_mdp_plane_sizes *ps);
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void mdss_mdp_data_calc_offset(struct mdss_mdp_data *data, u16 x, u16 y,
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struct mdss_mdp_plane_sizes *ps, struct mdss_mdp_format_params *fmt);
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void mdss_mdp_format_flag_removal(u32 *table, u32 num, u32 remove_bits);
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struct mdss_mdp_format_params *mdss_mdp_get_format_params(u32 format);
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int mdss_mdp_validate_offset_for_ubwc_format(
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struct mdss_mdp_format_params *fmt, u16 x, u16 y);
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void mdss_mdp_get_v_h_subsample_rate(u8 chroma_samp,
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u8 *v_sample, u8 *h_sample);
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struct mult_factor *mdss_mdp_get_comp_factor(u32 format,
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bool rt_factor);
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int mdss_mdp_data_map(struct mdss_mdp_data *data, bool rotator, int dir);
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void mdss_mdp_data_free(struct mdss_mdp_data *data, bool rotator, int dir);
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int mdss_mdp_data_get_and_validate_size(struct mdss_mdp_data *data,
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struct msmfb_data *planes, int num_planes, u32 flags,
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struct device *dev, bool rotator, int dir,
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struct mdp_layer_buffer *buffer);
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u32 mdss_get_panel_framerate(struct msm_fb_data_type *mfd);
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int mdss_mdp_calc_phase_step(u32 src, u32 dst, u32 *out_phase);
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void mdss_mdp_intersect_rect(struct mdss_rect *res_rect,
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const struct mdss_rect *dst_rect,
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const struct mdss_rect *sci_rect);
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void mdss_mdp_crop_rect(struct mdss_rect *src_rect,
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struct mdss_rect *dst_rect,
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const struct mdss_rect *sci_rect);
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void rect_copy_mdss_to_mdp(struct mdp_rect *user, struct mdss_rect *kernel);
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void rect_copy_mdp_to_mdss(struct mdp_rect *user, struct mdss_rect *kernel);
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bool mdss_rect_overlap_check(struct mdss_rect *rect1, struct mdss_rect *rect2);
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void mdss_rect_split(struct mdss_rect *in_roi, struct mdss_rect *l_roi,
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struct mdss_rect *r_roi, u32 splitpoint);
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int mdss_mdp_wb_kickoff(struct msm_fb_data_type *mfd,
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struct mdss_mdp_commit_cb *commit_cb);
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int mdss_mdp_wb_ioctl_handler(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
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int mdss_mdp_get_ctl_mixers(u32 fb_num, u32 *mixer_id);
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u32 mdss_mdp_get_mixer_mask(u32 pipe_num, u32 stage);
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u32 mdss_mdp_get_mixer_extn_mask(u32 pipe_num, u32 stage);
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u32 mdss_mdp_get_mixercfg(struct mdss_mdp_mixer *mixer, bool extn);
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u32 mdss_mdp_fb_stride(u32 fb_index, u32 xres, int bpp);
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void mdss_check_dsi_ctrl_status(struct work_struct *work, uint32_t interval);
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int mdss_mdp_calib_config(struct mdp_calib_config_data *cfg, u32 *copyback);
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int mdss_mdp_calib_config_buffer(struct mdp_calib_config_buffer *cfg,
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u32 *copyback);
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int mdss_mdp_ctl_update_fps(struct mdss_mdp_ctl *ctl);
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int mdss_mdp_pipe_is_staged(struct mdss_mdp_pipe *pipe);
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int mdss_mdp_writeback_display_commit(struct mdss_mdp_ctl *ctl, void *arg);
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struct mdss_mdp_ctl *mdss_mdp_ctl_mixer_switch(struct mdss_mdp_ctl *ctl,
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u32 return_type);
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void mdss_mdp_set_roi(struct mdss_mdp_ctl *ctl,
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struct mdss_rect *l_roi, struct mdss_rect *r_roi);
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void mdss_mdp_mixer_update_pipe_map(struct mdss_mdp_ctl *master_ctl,
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int mixer_mux);
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int mdss_mdp_wb_set_format(struct msm_fb_data_type *mfd, u32 dst_format);
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int mdss_mdp_wb_get_format(struct msm_fb_data_type *mfd,
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struct mdp_mixer_cfg *mixer_cfg);
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void mdss_mdp_pipe_calc_pixel_extn(struct mdss_mdp_pipe *pipe);
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int mdss_mdp_wb_set_secure(struct msm_fb_data_type *mfd, int enable);
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int mdss_mdp_wb_get_secure(struct msm_fb_data_type *mfd, uint8_t *enable);
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void mdss_mdp_ctl_restore(bool locked);
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int mdss_mdp_ctl_reset(struct mdss_mdp_ctl *ctl, bool is_recovery);
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int mdss_mdp_wait_for_xin_halt(u32 xin_id, bool is_vbif_nrt);
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void mdss_mdp_set_ot_limit(struct mdss_mdp_set_ot_params *params);
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int mdss_mdp_cmd_set_autorefresh_mode(struct mdss_mdp_ctl *ctl, int frame_cnt);
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int mdss_mdp_cmd_get_autorefresh_mode(struct mdss_mdp_ctl *ctl);
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int mdss_mdp_ctl_cmd_set_autorefresh(struct mdss_mdp_ctl *ctl, int frame_cnt);
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int mdss_mdp_ctl_cmd_get_autorefresh(struct mdss_mdp_ctl *ctl);
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int mdss_mdp_pp_get_version(struct mdp_pp_feature_version *version);
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struct mdss_mdp_ctl *mdss_mdp_ctl_alloc(struct mdss_data_type *mdata,
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u32 off);
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int mdss_mdp_ctl_free(struct mdss_mdp_ctl *ctl);
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struct mdss_mdp_mixer *mdss_mdp_mixer_assign(u32 id, bool wb);
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struct mdss_mdp_mixer *mdss_mdp_mixer_alloc(
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struct mdss_mdp_ctl *ctl, u32 type, int mux, int rotator);
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int mdss_mdp_mixer_free(struct mdss_mdp_mixer *mixer);
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bool mdss_mdp_is_wb_mdp_intf(u32 num, u32 reg_index);
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struct mdss_mdp_writeback *mdss_mdp_wb_assign(u32 id, u32 reg_index);
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struct mdss_mdp_writeback *mdss_mdp_wb_alloc(u32 caps, u32 reg_index);
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void mdss_mdp_wb_free(struct mdss_mdp_writeback *wb);
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#if defined(CONFIG_FB_MSM_MDSS_SAMSUNG)
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void samsung_timing_engine_control(int enable);
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#endif
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void mdss_dsc_parameters_calc(struct dsc_desc *dsc, int width, int height);
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void mdss_mdp_ctl_dsc_setup(struct mdss_mdp_ctl *ctl,
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struct mdss_panel_info *pinfo);
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#endif /* MDSS_MDP_H */
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