466 lines
10 KiB
C
466 lines
10 KiB
C
/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "bimc-bwmon: " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/spinlock.h>
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#include "governor_bw_hwmon.h"
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#define GLB_INT_STATUS(m) ((m)->global_base + 0x100)
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#define GLB_INT_CLR(m) ((m)->global_base + 0x108)
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#define GLB_INT_EN(m) ((m)->global_base + 0x10C)
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#define MON_INT_STATUS(m) ((m)->base + 0x100)
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#define MON_INT_CLR(m) ((m)->base + 0x108)
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#define MON_INT_EN(m) ((m)->base + 0x10C)
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#define MON_EN(m) ((m)->base + 0x280)
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#define MON_CLEAR(m) ((m)->base + 0x284)
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#define MON_CNT(m) ((m)->base + 0x288)
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#define MON_THRES(m) ((m)->base + 0x290)
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#define MON_MASK(m) ((m)->base + 0x298)
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#define MON_MATCH(m) ((m)->base + 0x29C)
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struct bwmon_spec {
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bool wrap_on_thres;
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bool overflow;
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bool throt_adj;
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};
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struct bwmon {
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void __iomem *base;
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void __iomem *global_base;
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unsigned int mport;
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unsigned int irq;
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const struct bwmon_spec *spec;
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struct device *dev;
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struct bw_hwmon hw;
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u32 throttle_adj;
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};
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#define to_bwmon(ptr) container_of(ptr, struct bwmon, hw)
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#define ENABLE_MASK BIT(0)
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#define THROTTLE_MASK 0x1F
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#define THROTTLE_SHIFT 16
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static DEFINE_SPINLOCK(glb_lock);
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static void mon_enable(struct bwmon *m)
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{
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writel_relaxed((ENABLE_MASK | m->throttle_adj), MON_EN(m));
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}
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static void mon_disable(struct bwmon *m)
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{
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writel_relaxed(m->throttle_adj, MON_EN(m));
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/*
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* mon_disable() and mon_irq_clear(),
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* If latter goes first and count happen to trigger irq, we would
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* have the irq line high but no one handling it.
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*/
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mb();
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}
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static void mon_clear(struct bwmon *m)
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{
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writel_relaxed(0x1, MON_CLEAR(m));
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/*
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* The counter clear and IRQ clear bits are not in the same 4KB
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* region. So, we need to make sure the counter clear is completed
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* before we try to clear the IRQ or do any other counter operations.
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*/
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mb();
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}
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static void mon_irq_enable(struct bwmon *m)
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{
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u32 val;
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spin_lock(&glb_lock);
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val = readl_relaxed(GLB_INT_EN(m));
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val |= 1 << m->mport;
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writel_relaxed(val, GLB_INT_EN(m));
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spin_unlock(&glb_lock);
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val = readl_relaxed(MON_INT_EN(m));
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val |= 0x1;
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writel_relaxed(val, MON_INT_EN(m));
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/*
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* make Sure irq enable complete for local and global
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* to avoid race with other monitor calls
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*/
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mb();
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}
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static void mon_irq_disable(struct bwmon *m)
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{
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u32 val;
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spin_lock(&glb_lock);
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val = readl_relaxed(GLB_INT_EN(m));
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val &= ~(1 << m->mport);
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writel_relaxed(val, GLB_INT_EN(m));
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spin_unlock(&glb_lock);
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val = readl_relaxed(MON_INT_EN(m));
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val &= ~0x1;
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writel_relaxed(val, MON_INT_EN(m));
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/*
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* make Sure irq disable complete for local and global
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* to avoid race with other monitor calls
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*/
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mb();
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}
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static unsigned int mon_irq_status(struct bwmon *m)
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{
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u32 mval;
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mval = readl_relaxed(MON_INT_STATUS(m));
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dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval,
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readl_relaxed(GLB_INT_STATUS(m)));
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return mval;
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}
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static void mon_irq_clear(struct bwmon *m)
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{
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writel_relaxed(0x3, MON_INT_CLR(m));
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mb();
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writel_relaxed(1 << m->mport, GLB_INT_CLR(m));
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mb();
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}
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static int mon_set_throttle_adj(struct bw_hwmon *hw, uint adj)
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{
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struct bwmon *m = to_bwmon(hw);
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if (adj > THROTTLE_MASK)
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return -EINVAL;
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adj = (adj & THROTTLE_MASK) << THROTTLE_SHIFT;
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m->throttle_adj = adj;
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return 0;
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}
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static u32 mon_get_throttle_adj(struct bw_hwmon *hw)
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{
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struct bwmon *m = to_bwmon(hw);
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return m->throttle_adj >> THROTTLE_SHIFT;
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}
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static void mon_set_limit(struct bwmon *m, u32 count)
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{
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writel_relaxed(count, MON_THRES(m));
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dev_dbg(m->dev, "Thres: %08x\n", count);
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}
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static u32 mon_get_limit(struct bwmon *m)
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{
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return readl_relaxed(MON_THRES(m));
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}
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#define THRES_HIT(status) (status & BIT(0))
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#define OVERFLOW(status) (status & BIT(1))
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static unsigned long mon_get_count(struct bwmon *m)
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{
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unsigned long count, status;
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count = readl_relaxed(MON_CNT(m));
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status = mon_irq_status(m);
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dev_dbg(m->dev, "Counter: %08lx\n", count);
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if (OVERFLOW(status) && m->spec->overflow)
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count += 0xFFFFFFFF;
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if (THRES_HIT(status) && m->spec->wrap_on_thres)
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count += mon_get_limit(m);
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dev_dbg(m->dev, "Actual Count: %08lx\n", count);
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return count;
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}
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/* ********** CPUBW specific code ********** */
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/* Returns MBps of read/writes for the sampling window. */
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static unsigned int mbps_to_bytes(unsigned long mbps, unsigned int ms,
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unsigned int tolerance_percent)
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{
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mbps *= (100 + tolerance_percent) * ms;
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mbps /= 100;
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mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC);
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mbps *= SZ_1M;
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return mbps;
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}
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static unsigned long get_bytes_and_clear(struct bw_hwmon *hw)
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{
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struct bwmon *m = to_bwmon(hw);
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unsigned long count;
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mon_disable(m);
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count = mon_get_count(m);
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mon_clear(m);
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mon_irq_clear(m);
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mon_enable(m);
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return count;
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}
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static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes)
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{
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unsigned long count;
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u32 limit;
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struct bwmon *m = to_bwmon(hw);
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mon_disable(m);
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count = mon_get_count(m);
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mon_clear(m);
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mon_irq_clear(m);
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if (likely(!m->spec->wrap_on_thres))
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limit = bytes;
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else
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limit = max(bytes, 500000UL);
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mon_set_limit(m, limit);
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mon_enable(m);
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return count;
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}
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static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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{
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struct bwmon *m = dev;
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if (!mon_irq_status(m))
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return IRQ_NONE;
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if (bw_hwmon_sample_end(&m->hw) > 0)
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return IRQ_WAKE_THREAD;
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return IRQ_HANDLED;
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}
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static irqreturn_t bwmon_intr_thread(int irq, void *dev)
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{
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struct bwmon *m = dev;
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update_bw_hwmon(&m->hw);
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return IRQ_HANDLED;
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}
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static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
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{
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struct bwmon *m = to_bwmon(hw);
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u32 limit;
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int ret;
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ret = request_threaded_irq(m->irq, bwmon_intr_handler,
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bwmon_intr_thread,
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IRQF_ONESHOT | IRQF_SHARED,
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dev_name(m->dev), m);
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if (ret) {
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dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
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ret);
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return ret;
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}
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mon_disable(m);
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limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0);
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mon_set_limit(m, limit);
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mon_clear(m);
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mon_irq_clear(m);
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mon_irq_enable(m);
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mon_enable(m);
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return 0;
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}
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static void stop_bw_hwmon(struct bw_hwmon *hw)
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{
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struct bwmon *m = to_bwmon(hw);
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mon_irq_disable(m);
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free_irq(m->irq, m);
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mon_disable(m);
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mon_clear(m);
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mon_irq_clear(m);
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}
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static int suspend_bw_hwmon(struct bw_hwmon *hw)
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{
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struct bwmon *m = to_bwmon(hw);
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mon_irq_disable(m);
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free_irq(m->irq, m);
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mon_disable(m);
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mon_irq_clear(m);
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return 0;
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}
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static int resume_bw_hwmon(struct bw_hwmon *hw)
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{
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struct bwmon *m = to_bwmon(hw);
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int ret;
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mon_clear(m);
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ret = request_threaded_irq(m->irq, bwmon_intr_handler,
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bwmon_intr_thread,
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IRQF_ONESHOT | IRQF_SHARED,
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dev_name(m->dev), m);
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if (ret) {
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dev_err(m->dev, "Unable to register interrupt handler! (%d)\n",
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ret);
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return ret;
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}
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mon_irq_enable(m);
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mon_enable(m);
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return 0;
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}
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/*************************************************************************/
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static const struct bwmon_spec spec[] = {
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{ .wrap_on_thres = true, .overflow = false, .throt_adj = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = false},
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{ .wrap_on_thres = false, .overflow = true, .throt_adj = true},
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};
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static struct of_device_id match_table[] = {
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{ .compatible = "qcom,bimc-bwmon", .data = &spec[0] },
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{ .compatible = "qcom,bimc-bwmon2", .data = &spec[1] },
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{ .compatible = "qcom,bimc-bwmon3", .data = &spec[2] },
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{}
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};
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static int bimc_bwmon_driver_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct bwmon *m;
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const struct of_device_id *id;
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int ret;
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u32 data;
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m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL);
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if (!m)
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return -ENOMEM;
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m->dev = dev;
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ret = of_property_read_u32(dev->of_node, "qcom,mport", &data);
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if (ret) {
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dev_err(dev, "mport not found!\n");
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return ret;
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}
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m->mport = data;
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id = of_match_device(match_table, dev);
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if (!id) {
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dev_err(dev, "Unknown device type!\n");
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return -ENODEV;
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}
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m->spec = id->data;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
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if (!res) {
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dev_err(dev, "base not found!\n");
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return -EINVAL;
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}
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m->base = devm_ioremap(dev, res->start, resource_size(res));
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if (!m->base) {
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dev_err(dev, "Unable map base!\n");
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return -ENOMEM;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global_base");
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if (!res) {
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dev_err(dev, "global_base not found!\n");
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return -EINVAL;
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}
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m->global_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!m->global_base) {
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dev_err(dev, "Unable map global_base!\n");
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return -ENOMEM;
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}
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m->irq = platform_get_irq(pdev, 0);
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if (m->irq < 0) {
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dev_err(dev, "Unable to get IRQ number\n");
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return m->irq;
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}
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m->hw.of_node = of_parse_phandle(dev->of_node, "qcom,target-dev", 0);
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if (!m->hw.of_node)
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return -EINVAL;
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m->hw.start_hwmon = &start_bw_hwmon;
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m->hw.stop_hwmon = &stop_bw_hwmon;
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m->hw.suspend_hwmon = &suspend_bw_hwmon;
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m->hw.resume_hwmon = &resume_bw_hwmon;
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m->hw.get_bytes_and_clear = &get_bytes_and_clear;
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m->hw.set_thres = &set_thres;
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if (m->spec->throt_adj) {
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m->hw.set_throttle_adj = &mon_set_throttle_adj;
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m->hw.get_throttle_adj = &mon_get_throttle_adj;
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}
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ret = register_bw_hwmon(dev, &m->hw);
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if (ret) {
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dev_err(dev, "Dev BW hwmon registration failed\n");
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return ret;
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}
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return 0;
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}
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static struct platform_driver bimc_bwmon_driver = {
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.probe = bimc_bwmon_driver_probe,
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.driver = {
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.name = "bimc-bwmon",
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.of_match_table = match_table,
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.owner = THIS_MODULE,
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},
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};
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static int __init bimc_bwmon_init(void)
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{
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return platform_driver_register(&bimc_bwmon_driver);
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}
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module_init(bimc_bwmon_init);
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static void __exit bimc_bwmon_exit(void)
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{
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platform_driver_unregister(&bimc_bwmon_driver);
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}
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module_exit(bimc_bwmon_exit);
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MODULE_DESCRIPTION("BIMC bandwidth monitor driver");
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MODULE_LICENSE("GPL v2");
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