275 lines
7.4 KiB
C
275 lines
7.4 KiB
C
/*
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* linux/arch/arm/mach-clps711x/autcpu12.c
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*
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* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/plat-ram.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand-gpio.h>
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#include <linux/platform_device.h>
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#include <linux/basic_mmio_gpio.h>
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#include <mach/hardware.h>
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#include <asm/sizes.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "devices.h"
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/* NOR flash */
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#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE)
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/* Board specific hardware definitions */
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#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000)
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#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000)
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#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000)
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#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000)
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#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000)
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#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000)
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/* NVRAM */
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#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000)
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/* SmartMedia flash */
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#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
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#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
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/* Ethernet */
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#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
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#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
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/* NAND flash */
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#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
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#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
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#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
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#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
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#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4)
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/* LCD contrast digital potentiometer */
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#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
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#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
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#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
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static struct resource autcpu12_cs8900_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
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DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
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};
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static struct resource autcpu12_nand_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
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};
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static struct mtd_partition autcpu12_nand_parts[] __initdata = {
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{
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.name = "Flash partition 1",
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.offset = 0,
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.size = SZ_8M,
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},
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{
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.name = "Flash partition 2",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
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size_t sz)
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{
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switch (sz) {
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case SZ_16M:
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case SZ_32M:
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break;
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case SZ_64M:
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case SZ_128M:
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pdata->parts[0].size = SZ_16M;
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break;
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default:
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pr_warn("Unsupported SmartMedia device size %u\n", sz);
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break;
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}
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}
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static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
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.gpio_rdy = AUTCPU12_SMC_RDY,
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.gpio_nce = AUTCPU12_SMC_NCE,
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.gpio_ale = AUTCPU12_SMC_ALE,
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.gpio_cle = AUTCPU12_SMC_CLE,
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.gpio_nwp = -1,
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.chip_delay = 20,
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.parts = autcpu12_nand_parts,
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.num_parts = ARRAY_SIZE(autcpu12_nand_parts),
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.adjust_parts = autcpu12_adjust_parts,
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};
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static struct platform_device autcpu12_nand_pdev __initdata = {
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.name = "gpio-nand",
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.id = -1,
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.resource = autcpu12_nand_resource,
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.num_resources = ARRAY_SIZE(autcpu12_nand_resource),
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.dev = {
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.platform_data = &autcpu12_nand_pdata,
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},
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};
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static struct resource autcpu12_mmgpio_resource[] __initdata = {
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DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
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};
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static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
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.base = AUTCPU12_MMGPIO_BASE,
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.ngpio = 8,
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};
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static struct platform_device autcpu12_mmgpio_pdev __initdata = {
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.name = "basic-mmio-gpio",
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.id = -1,
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.resource = autcpu12_mmgpio_resource,
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.num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
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.dev = {
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.platform_data = &autcpu12_mmgpio_pdata,
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},
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};
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static const struct gpio autcpu12_gpios[] __initconst = {
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{ AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
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{ AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
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{ AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
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};
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static struct mtd_partition autcpu12_flash_partitions[] = {
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{
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.name = "NOR.0",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data autcpu12_flash_pdata = {
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.width = 4,
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.parts = autcpu12_flash_partitions,
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.nr_parts = ARRAY_SIZE(autcpu12_flash_partitions),
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};
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static struct resource autcpu12_flash_resources[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
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};
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static struct platform_device autcpu12_flash_pdev __initdata = {
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.name = "physmap-flash",
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.id = 0,
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.resource = autcpu12_flash_resources,
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.num_resources = ARRAY_SIZE(autcpu12_flash_resources),
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.dev = {
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.platform_data = &autcpu12_flash_pdata,
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},
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};
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static struct resource autcpu12_nvram_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
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};
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static struct platdata_mtd_ram autcpu12_nvram_pdata = {
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.bankwidth = 4,
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};
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static struct platform_device autcpu12_nvram_pdev __initdata = {
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.name = "mtd-ram",
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.id = 0,
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.resource = autcpu12_nvram_resource,
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.num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
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.dev = {
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.platform_data = &autcpu12_nvram_pdata,
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},
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};
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static void __init autcpu12_nvram_init(void)
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{
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void __iomem *nvram;
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unsigned int save[2];
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resource_size_t nvram_size = SZ_128K;
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/*
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* Check for 32K/128K
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* Read ofs 0K
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* Read ofs 64K
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* Write complement to ofs 64K
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* Read and check result on ofs 0K
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* Restore contents
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*/
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nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
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if (nvram) {
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save[0] = readl(nvram + 0);
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save[1] = readl(nvram + SZ_64K);
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writel(~save[0], nvram + SZ_64K);
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if (readl(nvram + 0) != save[0]) {
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writel(save[0], nvram + 0);
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nvram_size = SZ_32K;
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} else
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writel(save[1], nvram + SZ_64K);
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iounmap(nvram);
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autcpu12_nvram_resource[0].end =
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autcpu12_nvram_resource[0].start + nvram_size - 1;
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platform_device_register(&autcpu12_nvram_pdev);
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} else
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pr_err("Failed to remap NVRAM resource\n");
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}
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static void __init autcpu12_init(void)
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{
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clps711x_devices_init();
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platform_device_register(&autcpu12_flash_pdev);
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platform_device_register_simple("video-clps711x", 0, NULL, 0);
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platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
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ARRAY_SIZE(autcpu12_cs8900_resource));
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platform_device_register(&autcpu12_mmgpio_pdev);
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autcpu12_nvram_init();
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}
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static void __init autcpu12_init_late(void)
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{
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gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
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platform_device_register(&autcpu12_nand_pdev);
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}
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MACHINE_START(AUTCPU12, "autronix autcpu12")
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/* Maintainer: Thomas Gleixner */
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.atag_offset = 0x20000,
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.map_io = clps711x_map_io,
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.init_irq = clps711x_init_irq,
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.init_time = clps711x_timer_init,
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.init_machine = autcpu12_init,
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.init_late = autcpu12_init_late,
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.restart = clps711x_restart,
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MACHINE_END
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