317 lines
8.4 KiB
C
317 lines
8.4 KiB
C
/*
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* linux/arch/cris/arch-v32/kernel/time.c
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*
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* Copyright (C) 2003-2010 Axis Communications AB
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*
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*/
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#include <linux/timex.h>
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#include <linux/time.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/swap.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/cpufreq.h>
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#include <asm/types.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/timer_defs.h>
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#include <hwregs/intr_vect_defs.h>
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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#include <hwregs/clkgen_defs.h>
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#endif
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/* Watchdog defines */
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#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
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#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
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/* Number of 763 counts before watchdog bites */
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#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
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/* Register the continuos readonly timer available in FS and ARTPEC-3. */
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static cycle_t read_cont_rotime(struct clocksource *cs)
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{
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return (u32)REG_RD(timer, regi_timer0, r_time);
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}
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static struct clocksource cont_rotime = {
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.name = "crisv32_rotime",
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.rating = 300,
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.read = read_cont_rotime,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init etrax_init_cont_rotime(void)
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{
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clocksource_register_khz(&cont_rotime, 100000);
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return 0;
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}
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arch_initcall(etrax_init_cont_rotime);
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unsigned long timer_regs[NR_CPUS] =
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{
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regi_timer0,
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#ifdef CONFIG_SMP
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regi_timer2
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#endif
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};
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extern int set_rtc_mmss(unsigned long nowtime);
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#ifdef CONFIG_CPU_FREQ
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static int
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cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
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void *data);
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static struct notifier_block cris_time_freq_notifier_block = {
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.notifier_call = cris_time_freq_notifier,
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};
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#endif
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unsigned long get_ns_in_jiffie(void)
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{
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reg_timer_r_tmr0_data data;
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unsigned long ns;
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data = REG_RD(timer, regi_timer0, r_tmr0_data);
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ns = (TIMER0_DIV - data) * 10;
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return ns;
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}
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/* From timer MDS describing the hardware watchdog:
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* 4.3.1 Watchdog Operation
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* The watchdog timer is an 8-bit timer with a configurable start value.
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* Once started the watchdog counts downwards with a frequency of 763 Hz
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* (100/131072 MHz). When the watchdog counts down to 1, it generates an
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* NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
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* chip.
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*/
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/* This gives us 1.3 ms to do something useful when the NMI comes */
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/* Right now, starting the watchdog is the same as resetting it */
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#define start_watchdog reset_watchdog
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#if defined(CONFIG_ETRAX_WATCHDOG)
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static short int watchdog_key = 42; /* arbitrary 7 bit number */
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#endif
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/* Number of pages to consider "out of memory". It is normal that the memory
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* is used though, so set this really low. */
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#define WATCHDOG_MIN_FREE_PAGES 8
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void reset_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
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/* Only keep watchdog happy as long as we have memory left! */
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if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
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/* Reset the watchdog with the inverse of the old key */
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/* Invert key, which is 7 bits */
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watchdog_key ^= ETRAX_WD_KEY_MASK;
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wd_ctrl.cnt = ETRAX_WD_CNT;
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wd_ctrl.cmd = regk_timer_start;
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wd_ctrl.key = watchdog_key;
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REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
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}
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#endif
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}
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/* stop the watchdog - we still need the correct key */
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void stop_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
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watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
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wd_ctrl.cnt = ETRAX_WD_CNT;
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wd_ctrl.cmd = regk_timer_stop;
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wd_ctrl.key = watchdog_key;
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REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
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#endif
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}
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extern void show_registers(struct pt_regs *regs);
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void handle_watchdog_bite(struct pt_regs *regs)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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extern int cause_of_death;
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oops_in_progress = 1;
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printk(KERN_WARNING "Watchdog bite\n");
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/* Check if forced restart or unexpected watchdog */
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if (cause_of_death == 0xbedead) {
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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/* There is a bug in Artpec-3 (voodoo TR 78) that requires
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* us to go to lower frequency for the reset to be reliable
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*/
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reg_clkgen_rw_clk_ctrl ctrl =
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REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
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ctrl.pll = 0;
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REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
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#endif
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while(1);
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}
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/* Unexpected watchdog, stop the watchdog and dump registers. */
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stop_watchdog();
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printk(KERN_WARNING "Oops: bitten by watchdog\n");
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show_registers(regs);
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oops_in_progress = 0;
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#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
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reset_watchdog();
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#endif
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while(1) /* nothing */;
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#endif
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}
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "xtime_update()" routine every clocktick.
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*/
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extern void cris_do_profile(struct pt_regs *regs);
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static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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int cpu = smp_processor_id();
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reg_timer_r_masked_intr masked_intr;
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reg_timer_rw_ack_intr ack_intr = { 0 };
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/* Check if the timer interrupt is for us (a tmr0 int) */
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masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
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if (!masked_intr.tmr0)
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return IRQ_NONE;
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/* Acknowledge the timer irq. */
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ack_intr.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
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/* Reset watchdog otherwise it resets us! */
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reset_watchdog();
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/* Update statistics. */
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update_process_times(user_mode(regs));
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cris_do_profile(regs); /* Save profiling information */
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/* The master CPU is responsible for the time keeping. */
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if (cpu != 0)
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return IRQ_HANDLED;
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/* Call the real timer interrupt handler */
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xtime_update(1);
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return IRQ_HANDLED;
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}
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/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
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static struct irqaction irq_timer = {
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.handler = timer_interrupt,
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.flags = IRQF_SHARED,
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.name = "timer"
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};
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void __init cris_timer_init(void)
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{
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int cpu = smp_processor_id();
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reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
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reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
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reg_timer_rw_intr_mask timer_intr_mask;
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/* Setup the etrax timers.
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* Base frequency is 100MHz, divider 1000000 -> 100 HZ
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* We use timer0, so timer1 is free.
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* The trig timer is used by the fasttimer API if enabled.
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*/
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tmr0_ctrl.op = regk_timer_ld;
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tmr0_ctrl.freq = regk_timer_f100;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
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tmr0_ctrl.op = regk_timer_run;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
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/* Enable the timer irq. */
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timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
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timer_intr_mask.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
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}
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void __init time_init(void)
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{
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reg_intr_vect_rw_mask intr_mask;
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/* Probe for the RTC and read it if it exists.
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* Before the RTC can be probed the loops_per_usec variable needs
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* to be initialized to make usleep work. A better value for
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* loops_per_usec is calculated by the kernel later once the
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* clock has started.
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*/
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loops_per_usec = 50;
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/* Start CPU local timer. */
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cris_timer_init();
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/* Enable the timer irq in global config. */
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intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
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intr_mask.timer0 = 1;
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REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
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/* Now actually register the timer irq handler that calls
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* timer_interrupt(). */
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setup_irq(TIMER0_INTR_VECT, &irq_timer);
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/* Enable watchdog if we should use one. */
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#if defined(CONFIG_ETRAX_WATCHDOG)
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printk(KERN_INFO "Enabling watchdog...\n");
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start_watchdog();
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/* If we use the hardware watchdog, we want to trap it as an NMI
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* and dump registers before it resets us. For this to happen, we
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* must set the "m" NMI enable flag (which once set, is unset only
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* when an NMI is taken). */
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{
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unsigned long flags;
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local_save_flags(flags);
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flags |= (1<<30); /* NMI M flag is at bit 30 */
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local_irq_restore(flags);
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}
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#endif
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#ifdef CONFIG_CPU_FREQ
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cpufreq_register_notifier(&cris_time_freq_notifier_block,
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CPUFREQ_TRANSITION_NOTIFIER);
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#endif
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}
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#ifdef CONFIG_CPU_FREQ
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static int
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cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct cpufreq_freqs *freqs = data;
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if (val == CPUFREQ_POSTCHANGE) {
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reg_timer_r_tmr0_data data;
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reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
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do {
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data = REG_RD(timer, timer_regs[freqs->cpu],
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r_tmr0_data);
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} while (data > 20);
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REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
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}
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return 0;
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}
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#endif
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