598 lines
17 KiB
C
598 lines
17 KiB
C
/*
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* muic_regmap_s2mm001.c
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*
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* Copyright (C) 2014 Samsung Electronics
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* N S SABIN <n.sabin@samsung.com>
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* THOMAS RYU <smilesr.ryu@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/host_notify.h>
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#include <linux/string.h>
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#include <linux/muic/muic.h>
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#if defined(CONFIG_MUIC_NOTIFIER)
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#include <linux/muic/muic_notifier.h>
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#endif /* CONFIG_MUIC_NOTIFIER */
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#if defined(CONFIG_OF)
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#endif /* CONFIG_OF */
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#include "muic-internal.h"
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#include "muic_i2c.h"
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#include "muic_regmap.h"
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#define ADC_DETECT_TIME_200MS (0x03)
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#define KEY_PRESS_TIME_100MS (0x00)
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/* S2MM001 Timing Set 1 & 2 register Timing table */
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#define OCP_TIME_DELAY_1MS (0x00)
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#define OCP_TIME_DELAY_2MS (0x01)
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#define OCP_TIME_DELAY_4MS (0x02)
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#define OCP_TIME_DELAY_8MS (0x03)
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#define OCP_TIME_DELAY_12MS (0x04)
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#define OCP_TIME_DELAY_16MS (0x05)
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#define KEY_PRESS_TIME_100MS (0x00)
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#define KEY_PRESS_TIME_200MS (0x10)
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#define KEY_PRESS_TIME_300MS (0x20)
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#define KEY_PRESS_TIME_700MS (0x60)
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#define LONGKEY_PRESS_TIME_300MS (0x00)
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#define LONGKEY_PRESS_TIME_500MS (0x02)
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#define LONGKEY_PRESS_TIME_1000MS (0x07)
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#define LONGKEY_PRESS_TIME_1500MS (0x0C)
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#define SWITCHING_WAIT_TIME_10MS (0x00)
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#define SWITCHING_WAIT_TIME_210MS (0xa0)
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enum s2mm001_muic_reg_init_value {
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REG_INTMASK1_VALUE = (0xDC),
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REG_INTMASK2_VALUE = (0x20),
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REG_INTMASK2_VBUS = (0x02),
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REG_TIMING1_VALUE = (OCP_TIME_DELAY_4MS |
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KEY_PRESS_TIME_200MS),
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};
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/* s2mm001 I2C registers */
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enum s2mm001_muic_reg {
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REG_DEVID = 0x01,
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REG_CTRL = 0x02,
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REG_INT1 = 0x03,
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REG_INT2 = 0x04,
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REG_INTMASK1 = 0x05,
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REG_INTMASK2 = 0x06,
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REG_ADC = 0x07,
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REG_TIMING1 = 0x08,
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REG_TIMING2 = 0x09,
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/* unused registers */
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REG_DEVT1 = 0x0a,
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REG_DEVT2 = 0x0b,
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REG_BTN1 = 0x0c,
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REG_BTN2 = 0x0d,
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REG_MUIC_STATUS = 0x0e,
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REG_MANSW1 = 0x13,
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REG_MANSW2 = 0x14,
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REG_DEVT3 = 0x15,
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REG_RESET = 0x1B,
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REG_TIMING3 = 0x20,
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REG_OCP_SET = 0x22,
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REG_MUIC_CTRL = 0x23,
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REG_END,
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};
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#define REG_ITEM(addr, bitp, mask) ((bitp<<16) | (mask<<8) | addr)
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/* Field */
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enum s2mm001_muic_reg_item {
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DEVID_VERSION = REG_ITEM(REG_DEVID, _BIT3, _MASK5),
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DEVID_VendorID = REG_ITEM(REG_DEVID, _BIT0, _MASK3),
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CTRL_SW_OPEN = REG_ITEM(REG_CTRL, _BIT4, _MASK1),
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CTRL_RAWDATA = REG_ITEM(REG_CTRL, _BIT3, _MASK1),
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CTRL_ManualSW = REG_ITEM(REG_CTRL, _BIT2, _MASK1),
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CTRL_WAIT = REG_ITEM(REG_CTRL, _BIT1, _MASK1),
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CTRL_MASK_INT = REG_ITEM(REG_CTRL, _BIT0, _MASK1),
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INT1_OVP_OCP_DIS = REG_ITEM(REG_INT1, _BIT7, _MASK1),
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INT1_OCP_EVENT = REG_ITEM(REG_INT1, _BIT6, _MASK1),
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INT1_OVP_EVENT = REG_ITEM(REG_INT1, _BIT5, _MASK1),
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INT1_DETACH = REG_ITEM(REG_INT1, _BIT1, _MASK1),
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INT1_ATTACH = REG_ITEM(REG_INT1, _BIT0, _MASK1),
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INT2_RID_CHARGER = REG_ITEM(REG_INT2, _BIT6, _MASK1),
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INT2_MHL = REG_ITEM(REG_INT2, _BIT5, _MASK1),
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INT2_ADC_CHG = REG_ITEM(REG_INT2, _BIT2, _MASK1),
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INT2_VBUS_OFF = REG_ITEM(REG_INT2, _BIT0, _MASK1),
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INTMASK1_OVP_OCP_DIS_M = REG_ITEM(REG_INTMASK1, _BIT7, _MASK1),
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INTMASK1_OCP_EVENT_M = REG_ITEM(REG_INTMASK1, _BIT5, _MASK1),
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INTMASK1_OVP_EVENT_M = REG_ITEM(REG_INTMASK1, _BIT5, _MASK1),
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INTMASK1_DETACH_M = REG_ITEM(REG_INTMASK1, _BIT1, _MASK1),
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INTMASK1_ATTACH_M = REG_ITEM(REG_INTMASK1, _BIT0, _MASK1),
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INTMASK2_RID_CHARGERM = REG_ITEM(REG_INTMASK2, _BIT6, _MASK1),
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INTMASK2_MHL_M = REG_ITEM(REG_INTMASK2, _BIT5, _MASK1),
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INTMASK2_ADC_CHG_M = REG_ITEM(REG_INTMASK2, _BIT2, _MASK1),
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INTMASK2_REV_ACCE_M = REG_ITEM(REG_INTMASK2, _BIT1, _MASK1),
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INTMASK2_VBUS_OFF_M = REG_ITEM(REG_INTMASK2, _BIT0, _MASK1),
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ADC_ADCERR = REG_ITEM(REG_ADC, _BIT7, _MASK1),
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ADC_ADC_VALUE = REG_ITEM(REG_ADC, _BIT0, _MASK5),
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TIMING1_KEY_PRESS_T = REG_ITEM(REG_TIMING1, _BIT4, _MASK4),
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TIMING1_OCP_TIME_DELAY = REG_ITEM(REG_TIMING1, _BIT0, _MASK3),
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TIMING2_SW_WAIT_T = REG_ITEM(REG_TIMING2, _BIT4, _MASK4),
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TIMING2_LONG_KEY_T = REG_ITEM(REG_TIMING2, _BIT0, _MASK4),
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DEVT1_USB_OTG = REG_ITEM(REG_DEVT1, _BIT7, _MASK1),
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DEVT1_DEDICATED_CHG = REG_ITEM(REG_DEVT1, _BIT6, _MASK1),
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DEVT1_USB_CHG = REG_ITEM(REG_DEVT1, _BIT5, _MASK1),
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DEVT1_CAR_KIT_CHARGER = REG_ITEM(REG_DEVT1, _BIT4, _MASK1),
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DEVT1_UART = REG_ITEM(REG_DEVT1, _BIT3, _MASK1),
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DEVT1_USB = REG_ITEM(REG_DEVT1, _BIT2, _MASK1),
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DEVT1_AUDIO_TYPE2 = REG_ITEM(REG_DEVT1, _BIT1, _MASK1),
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DEVT1_AUDIO_TYPE1 = REG_ITEM(REG_DEVT1, _BIT0, _MASK1),
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DEVT2_AV = REG_ITEM(REG_DEVT2, _BIT6, _MASK1),
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DEVT2_TTY = REG_ITEM(REG_DEVT2, _BIT5, _MASK1),
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DEVT2_PPD = REG_ITEM(REG_DEVT2, _BIT4, _MASK1),
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DEVT2_JIG_UART_OFF = REG_ITEM(REG_DEVT2, _BIT3, _MASK1),
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DEVT2_JIG_UART_ON = REG_ITEM(REG_DEVT2, _BIT2, _MASK1),
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DEVT2_JIG_USB_OFF = REG_ITEM(REG_DEVT2, _BIT1, _MASK1),
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DEVT2_JIG_USB_ON = REG_ITEM(REG_DEVT2, _BIT0, _MASK1),
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STATUS_DCDTMR_OUT = REG_ITEM(REG_MUIC_STATUS, _BIT5, _MASK1),
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STATUS_VBUSOVP = REG_ITEM(REG_MUIC_STATUS, _BIT4, _MASK1),
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STATUS_CARKIT_TYPE = REG_ITEM(REG_MUIC_STATUS, _BIT0, _MASK2),
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MANSW1_DM_CON_SW = REG_ITEM(REG_MANSW1, _BIT5, _MASK3),
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MANSW1_DP_CON_SW = REG_ITEM(REG_MANSW1, _BIT2, _MASK3),
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MANSW1_CHGIN_EN = REG_ITEM(REG_MANSW1, _BIT1, _MASK1),
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MANSW1_OTG_EN = REG_ITEM(REG_MANSW1, _BIT0, _MASK1),
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MANSW2_CHG_DET = REG_ITEM(REG_MANSW2, _BIT4, _MASK1),
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MANSW2_BOOT_SW = REG_ITEM(REG_MANSW2, _BIT3, _MASK1),
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MANSW2_JIG_ON = REG_ITEM(REG_MANSW2, _BIT2, _MASK1),
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MANSW2_IDBSW = REG_ITEM(REG_MANSW2, _BIT1, _MASK1),
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DEVT3_AV75 = REG_ITEM(REG_DEVT3, _BIT7, _MASK1),
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DEVT3_U200_CHG = REG_ITEM(REG_DEVT3, _BIT6, _MASK1),
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DEVT3_APPLECHG = REG_ITEM(REG_DEVT3, _BIT5, _MASK1),
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DEVT3_AV_CABLE_VBUS = REG_ITEM(REG_DEVT3, _BIT4, _MASK1),
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DEVT3_VBUS_NONSTD = REG_ITEM(REG_DEVT3, _BIT2, _MASK1),
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DEVT3_VBUS_VALID = REG_ITEM(REG_DEVT3, _BIT1, _MASK1),
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DEVT3_MHL = REG_ITEM(REG_DEVT3, _BIT0, _MASK1),
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RESET_RESET = REG_ITEM(REG_RESET, _BIT0, _MASK1),
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TIMING3_ADC_PERIOD = REG_ITEM(REG_TIMING3, _BIT4, _MASK2),
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TIMING3_LOADSW_ENTIME = REG_ITEM(REG_TIMING3, _BIT3, _MASK1),
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TIMING3_DCDTMRSET = REG_ITEM(REG_TIMING3, _BIT1, _MASK2),
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OCPSET_OCP_SET = REG_ITEM(REG_OCP_SET, _BIT0, _MASK6),
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MUIC_CTRL_VBUS_DEC = REG_ITEM(REG_MUIC_CTRL, _BIT5, _MASK1),
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MUIC_ADC_OFF = REG_ITEM(REG_MUIC_CTRL, _BIT1, _MASK1),
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MUIC_CPEN = REG_ITEM(REG_MUIC_CTRL, _BIT1, _MASK1),
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};
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/* s2mm001 Control register */
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#define CTRL_SWITCH_OPEN_SHIFT 4
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#define CTRL_RAW_DATA_SHIFT 3
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#define CTRL_MANUAL_SW_SHIFT 2
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#define CTRL_WAIT_SHIFT 1
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#define CTRL_INT_MASK_SHIFT 0
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#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
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#define CTRL_RAW_DATA_MASK (0x1 << CTRL_RAW_DATA_SHIFT)
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#define CTRL_MANUAL_SW_MASK (0x1 << CTRL_MANUAL_SW_SHIFT)
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#define CTRL_WAIT_MASK (0x1 << CTRL_WAIT_SHIFT)
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#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
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#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | CTRL_RAW_DATA_MASK | \
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/*CTRL_MANUAL_SW_MASK |*/ CTRL_WAIT_MASK | \
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CTRL_INT_MASK_MASK)
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/* S2MM001_MUIC_REG_CTRL2 register */
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#define MUIC_CTRL_CHGPUMP_nEN (0x1 << 0)
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struct reg_value_set {
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int value;
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char *alias;
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};
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/* ADC Scan Mode Values : b'1 */
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static struct reg_value_set s2mm001_adc_scanmode_tbl[] = {
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[ADC_SCANMODE_CONTINUOUS] = {0x01, "Periodic"},
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[ADC_SCANMODE_ONESHOT] = {0x00, "Oneshot."},
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[ADC_SCANMODE_PULSE] = {0x00, "Oneshot.."},
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};
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/*
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* Manual Switch
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* D- [7:5] / D+ [4:2] / Vbus [1:0]
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* 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
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* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to VBout
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*/
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#define _D_OPEN (0x0)
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#define _D_USB (0x1)
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#define _D_AUDIO (0x2)
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#define _D_UART (0x3)
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#define _V_OPEN (0x0)
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#define _V_CHARGER (0x2)
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#define _V_OTG (0x1)
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/* COM patch Values */
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#define COM_VALUE(dm, vb) ((dm<<5) | (dm<<2) | vb)
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#define _COM_OPEN COM_VALUE(_D_OPEN, _V_OPEN)
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#define _COM_OPEN_WITH_V_BUS COM_VALUE(_D_OPEN, _V_CHARGER)
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#define _COM_UART_AP COM_VALUE(_D_UART, _V_CHARGER)
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#define _COM_UART_CP _COM_UART_AP
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#define _COM_USB_AP COM_VALUE(_D_USB, _V_CHARGER)
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#define _COM_USB_CP _COM_USB_AP
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#define _COM_AUDIO COM_VALUE(_D_AUDIO, _V_CHARGER)
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static int s2mm001_com_value_tbl[] = {
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[COM_OPEN] = _COM_OPEN,
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[COM_OPEN_WITH_V_BUS] = _COM_OPEN_WITH_V_BUS,
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[COM_UART_AP] = _COM_UART_AP,
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[COM_UART_CP] = _COM_UART_CP,
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[COM_USB_AP] = _COM_USB_AP,
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[COM_USB_CP] = _COM_USB_CP,
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[COM_AUDIO] = _COM_AUDIO,
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};
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#define REG_CTRL_INITIAL (CTRL_MASK | CTRL_MANUAL_SW_MASK)
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static regmap_t s2mm001_muic_regmap_table[] = {
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[REG_DEVID] = {"DeviceID", 0x00, 0x00, INIT_NONE},
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[REG_CTRL] = {"CONTROL", 0x1F, 0x00, REG_CTRL_INITIAL,},
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[REG_INT1] = {"INT1", 0x00, 0x00, INIT_NONE,},
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[REG_INT2] = {"INT2", 0x00, 0x00, INIT_NONE,},
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[REG_INTMASK1] = {"INTMASK1", 0x00, 0x00, REG_INTMASK1_VALUE,},
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[REG_INTMASK2] = {"INTMASK2", 0x00, 0x00, REG_INTMASK2_VALUE,},
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[REG_ADC] = {"ADC", 0x1F, 0x00, INIT_NONE,},
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[REG_TIMING1] = {"TimingSet1", 0x02, 0x00, REG_TIMING1_VALUE,},
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[REG_TIMING2] = {"TimingSet2", 0x00, 0x00, INIT_NONE,},
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[REG_DEVT1] = {"DEVICETYPE1", 0x00, 0x00, INIT_NONE,},
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[REG_DEVT2] = {"DEVICETYPE2", 0x00, 0x00, INIT_NONE,},
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[REG_BTN1] = {"BUTTON1", 0x00, 0x00, INIT_NONE,},
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[REG_BTN2] = {"BUTTON2", 0x00, 0x00, INIT_NONE,},
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[REG_MUIC_STATUS] = {"MUIC_STATUS", 0x00, 0x00, INIT_NONE,},
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/* 0x0F ~ 0x12: Reserved */
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[REG_MANSW1] = {"ManualSW1", 0x00, 0x00, INIT_NONE,},
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[REG_MANSW2] = {"ManualSW2", 0x00, 0x00, INIT_NONE,},
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[REG_DEVT3] = {"DEVICETYPE3", 0x00, 0x00, INIT_NONE,},
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/* 0x16 ~ 0x1A: Reserved */
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[REG_RESET] = {"RESET", 0x00, 0x00, INIT_NONE,},
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/* 0x1C: Reserved */
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[REG_TIMING3] = {"TimingSet3", 0x14, 0x00, INIT_NONE,},
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/* 0x1E ~ 0x1F: Reserved */
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[REG_OCP_SET] = {"OCP_SET", 0x29, 0x00, INIT_NONE,},
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[REG_MUIC_CTRL] = {"MUIC_CTRL", 0x00, 0x00, MUIC_CTRL_CHGPUMP_nEN,},
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[REG_END] = {NULL, 0, 0, INIT_NONE},
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};
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static int s2mm001_muic_ioctl(struct regmap_desc *pdesc,
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int arg1, int *arg2, int *arg3)
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{
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int ret = 0;
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switch (arg1) {
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case GET_COM_VAL:
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*arg2 = s2mm001_com_value_tbl[*arg2];
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*arg3 = REG_MANSW1;
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break;
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case GET_CTLREG:
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*arg3 = REG_CTRL;
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break;
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case GET_ADC:
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*arg3 = ADC_ADC_VALUE;
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break;
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case GET_SWITCHING_MODE:
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*arg3 = CTRL_ManualSW;
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break;
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case GET_INT_MASK:
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*arg3 = CTRL_MASK_INT;
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break;
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case GET_REVISION:
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*arg3 = DEVID_VendorID;
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break;
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case GET_OTG_STATUS:
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*arg3 = INTMASK2_VBUS_OFF_M;
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break;
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default:
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ret = -1;
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break;
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}
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if (pdesc->trace) {
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pr_info("%s: ret:%d arg1:%x,", __func__, ret, arg1);
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if (arg2)
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pr_info(" arg2:%x,", *arg2);
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if (arg3)
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pr_info(" arg3:%x - %s", *arg3,
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regmap_to_name(pdesc, _ATTR_ADDR(*arg3)));
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pr_info("\n");
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}
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return ret;
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}
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static int s2mm001_attach_ta(struct regmap_desc *pdesc)
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{
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int attr = 0, value = 0, ret = 0;
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pr_info("%s\n", __func__);
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do {
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attr = REG_MANSW1 | _ATTR_OVERWRITE_M;
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value = _COM_OPEN_WITH_V_BUS;
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ret = regmap_write_value(pdesc, attr, value);
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if (ret < 0) {
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pr_err("%s REG_MANSW1 write fail.\n", __func__);
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break;
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}
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_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
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attr = REG_MANSW2 | _ATTR_OVERWRITE_M;
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value = 0x10; /* CHG_DET low */
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ret = regmap_write_value(pdesc, attr, value);
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if (ret < 0) {
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pr_err("%s REG_MANSW2 write fail.\n", __func__);
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break;
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}
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_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
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attr = CTRL_ManualSW;
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value = 0; /* manual switching mode */
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ret = regmap_write_value(pdesc, attr, value);
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if (ret < 0) {
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pr_err("%s REG_CTRL write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
} while (0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int s2mm001_detach_ta(struct regmap_desc *pdesc)
|
|
{
|
|
int attr = 0, value = 0, ret = 0;
|
|
|
|
pr_info("%s\n", __func__);
|
|
|
|
do {
|
|
attr = REG_MANSW1 | _ATTR_OVERWRITE_M;
|
|
value = _COM_OPEN;
|
|
ret = regmap_write_value(pdesc, attr, value);
|
|
if (ret < 0) {
|
|
pr_err("%s REG_MANSW1 write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
|
|
attr = REG_MANSW2 | _ATTR_OVERWRITE_M;
|
|
value = 0x00;
|
|
ret = regmap_write_value(pdesc, attr, value);
|
|
if (ret < 0) {
|
|
pr_err("%s REG_MANSW2 write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
|
|
attr = CTRL_ManualSW;
|
|
value = 1; /* auto switching mode */
|
|
ret = regmap_write_value(pdesc, attr, value);
|
|
if (ret < 0) {
|
|
pr_err("%s REG_CTRL write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
|
|
} while (0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int s2mm001_set_rustproof(struct regmap_desc *pdesc, int op)
|
|
{
|
|
int attr = 0, value = 0, ret = 0;
|
|
|
|
pr_info("%s\n", __func__);
|
|
|
|
do {
|
|
attr = MANSW2_JIG_ON;
|
|
value = op ? 1 : 0;
|
|
ret = regmap_write_value(pdesc, attr, value);
|
|
if (ret < 0) {
|
|
pr_err("%s MANSW2_JIG_ON write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
|
|
attr = CTRL_ManualSW;
|
|
value = op ? 0 : 1;
|
|
ret = regmap_write_value(pdesc, attr, value);
|
|
if (ret < 0) {
|
|
pr_err("%s CTRL_ManualSW write fail.\n", __func__);
|
|
break;
|
|
}
|
|
|
|
_REGMAP_TRACE(pdesc, 'w', ret, attr, value);
|
|
|
|
} while (0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int s2mm001_get_vps_data(struct regmap_desc *pdesc, void *pbuf)
|
|
{
|
|
muic_data_t *pmuic = pdesc->muic;
|
|
vps_data_t *pvps = (vps_data_t *)pbuf;
|
|
int attr;
|
|
|
|
if (pdesc->trace)
|
|
pr_info("%s\n", __func__);
|
|
|
|
*(u8 *)&pvps->s.val1 = muic_i2c_read_byte(pmuic->i2c, REG_DEVT1);
|
|
*(u8 *)&pvps->s.val2 = muic_i2c_read_byte(pmuic->i2c, REG_DEVT2);
|
|
*(u8 *)&pvps->s.val3 = muic_i2c_read_byte(pmuic->i2c, REG_DEVT3);
|
|
|
|
attr = DEVT3_VBUS_VALID;
|
|
*(u8 *)&pvps->s.vbvolt = regmap_read_value(pdesc, attr);
|
|
|
|
attr = ADC_ADC_VALUE;
|
|
*(u8 *)&pvps->s.adc = regmap_read_value(pdesc, attr);
|
|
|
|
return 0;
|
|
}
|
|
/*
|
|
static int s2mm001_muic_enable_accdet(struct regmap_desc *pdesc)
|
|
{
|
|
int ret = 0;
|
|
return ret;
|
|
}
|
|
static int s2mm001_muic_disable_accdet(struct regmap_desc *pdesc)
|
|
{
|
|
int ret = 0;
|
|
return ret;
|
|
}
|
|
*/
|
|
static int s2mm001_get_adc_scan_mode(struct regmap_desc *pdesc)
|
|
{
|
|
pr_info("%s: Not implemented.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static void s2mm001_set_adc_scan_mode(struct regmap_desc *pdesc, const int mode)
|
|
{
|
|
pr_info("%s: Not implemented.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
enum switching_mode_val{
|
|
_SWMODE_AUTO =1,
|
|
_SWMODE_MANUAL =0,
|
|
};
|
|
|
|
static int s2mm001_get_switching_mode(struct regmap_desc *pdesc)
|
|
{
|
|
pr_info("%s: Not implemented.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static void s2mm001_set_switching_mode(struct regmap_desc *pdesc, int mode)
|
|
{
|
|
pr_info("%s: Not implemented.\n", __func__);
|
|
return 0;
|
|
}
|
|
static void s2mm001_get_fromatted_dump(struct regmap_desc *pdesc, char *mesg)
|
|
{
|
|
muic_data_t *muic = pdesc->muic;
|
|
int val;
|
|
|
|
if (pdesc->trace)
|
|
pr_info("%s\n", __func__);
|
|
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_CTRL);
|
|
sprintf(mesg, "CT:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_INTMASK1);
|
|
sprintf(mesg+strlen(mesg), "IM1:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_INTMASK2);
|
|
sprintf(mesg+strlen(mesg), "IM2:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_MANSW1);
|
|
sprintf(mesg+strlen(mesg), "MS1:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_MANSW2);
|
|
sprintf(mesg+strlen(mesg), "MS2:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_ADC);
|
|
sprintf(mesg+strlen(mesg), "ADC:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_DEVT1);
|
|
sprintf(mesg+strlen(mesg), "DT1:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_DEVT2);
|
|
sprintf(mesg+strlen(mesg), "DT2:%x ", val);
|
|
val = i2c_smbus_read_byte_data(muic->i2c, REG_DEVT3);
|
|
sprintf(mesg+strlen(mesg), "DT3:%x ", val);
|
|
}
|
|
|
|
static int s2mm001_get_sizeof_regmap(void)
|
|
{
|
|
pr_info("%s:%s\n", MUIC_DEV_NAME, __func__);
|
|
return (int)ARRAY_SIZE(s2mm001_muic_regmap_table);
|
|
}
|
|
|
|
static struct regmap_ops s2mm001_muic_regmap_ops = {
|
|
.get_size = s2mm001_get_sizeof_regmap,
|
|
.ioctl = s2mm001_muic_ioctl,
|
|
.get_formatted_dump = s2mm001_get_fromatted_dump,
|
|
};
|
|
|
|
static struct vendor_ops s2mm001_muic_vendor_ops = {
|
|
.attach_ta = s2mm001_attach_ta,
|
|
.detach_ta = s2mm001_detach_ta,
|
|
.get_switch = sm5703_get_switching_mode,
|
|
.set_switch = sm5703_set_switching_mode,
|
|
.set_adc_scan_mode = sm5703_set_adc_scan_mode,
|
|
.get_adc_scan_mode = sm5703_get_adc_scan_mode,
|
|
.set_rustproof = s2mm001_set_rustproof,
|
|
.get_vps_data = s2mm001_get_vps_data,
|
|
};
|
|
|
|
static struct regmap_desc s2mm001_muic_regmap_desc = {
|
|
.name = "s2mm001-MUIC",
|
|
.regmap = s2mm001_muic_regmap_table,
|
|
.size = REG_END,
|
|
.regmapops = &s2mm001_muic_regmap_ops,
|
|
.vendorops = &s2mm001_muic_vendor_ops,
|
|
};
|
|
|
|
void muic_register_s2mm001_regmap_desc(struct regmap_desc **pdesc)
|
|
{
|
|
*pdesc = &s2mm001_muic_regmap_desc;
|
|
}
|