648 lines
18 KiB
C
648 lines
18 KiB
C
/*
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* ams AS3722 pin control and GPIO driver.
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*
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* Copyright (c) 2013, NVIDIA Corporation.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
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* whether express or implied; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307, USA
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*/
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mfd/as3722.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include "core.h"
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#include "pinconf.h"
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#include "pinctrl-utils.h"
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#define AS3722_PIN_GPIO0 0
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#define AS3722_PIN_GPIO1 1
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#define AS3722_PIN_GPIO2 2
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#define AS3722_PIN_GPIO3 3
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#define AS3722_PIN_GPIO4 4
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#define AS3722_PIN_GPIO5 5
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#define AS3722_PIN_GPIO6 6
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#define AS3722_PIN_GPIO7 7
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#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
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#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
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#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
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#define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
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#define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
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struct as3722_pin_function {
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const char *name;
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const char * const *groups;
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unsigned ngroups;
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int mux_option;
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};
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struct as3722_gpio_pin_control {
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unsigned mode_prop;
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int io_function;
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};
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struct as3722_pingroup {
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const char *name;
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const unsigned pins[1];
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unsigned npins;
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};
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struct as3722_pctrl_info {
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struct device *dev;
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struct pinctrl_dev *pctl;
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struct as3722 *as3722;
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struct gpio_chip gpio_chip;
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int pins_current_opt[AS3722_PIN_NUM];
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const struct as3722_pin_function *functions;
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unsigned num_functions;
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const struct as3722_pingroup *pin_groups;
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int num_pin_groups;
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const struct pinctrl_pin_desc *pins;
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unsigned num_pins;
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struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
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};
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static const struct pinctrl_pin_desc as3722_pins_desc[] = {
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PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
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PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
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PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
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PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
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PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
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PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
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PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
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PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
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};
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static const char * const gpio_groups[] = {
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"gpio0",
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"gpio1",
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"gpio2",
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"gpio3",
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"gpio4",
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"gpio5",
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"gpio6",
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"gpio7",
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};
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enum as3722_pinmux_option {
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AS3722_PINMUX_GPIO = 0,
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AS3722_PINMUX_INTERRUPT_OUT = 1,
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AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
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AS3722_PINMUX_GPIO_INTERRUPT = 3,
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AS3722_PINMUX_PWM_INPUT = 4,
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AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
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AS3722_PINMUX_OC_PG_SD0 = 6,
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AS3722_PINMUX_PG_OUT = 7,
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AS3722_PINMUX_CLK32K_OUT = 8,
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AS3722_PINMUX_WATCHDOG_INPUT = 9,
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AS3722_PINMUX_SOFT_RESET_IN = 11,
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AS3722_PINMUX_PWM_OUTPUT = 12,
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AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
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AS3722_PINMUX_OC_PG_SD6 = 14,
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};
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#define FUNCTION_GROUP(fname, mux) \
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{ \
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.name = #fname, \
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.groups = gpio_groups, \
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.ngroups = ARRAY_SIZE(gpio_groups), \
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.mux_option = AS3722_PINMUX_##mux, \
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}
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static const struct as3722_pin_function as3722_pin_function[] = {
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FUNCTION_GROUP(gpio, GPIO),
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FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
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FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
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FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
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FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
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FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
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FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
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FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
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FUNCTION_GROUP(powergood-out, PG_OUT),
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FUNCTION_GROUP(pwm-in, PWM_INPUT),
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FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
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FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
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FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
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FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
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};
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#define AS3722_PINGROUP(pg_name, pin_id) \
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{ \
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.name = #pg_name, \
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.pins = {AS3722_PIN_##pin_id}, \
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.npins = 1, \
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}
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static const struct as3722_pingroup as3722_pingroups[] = {
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AS3722_PINGROUP(gpio0, GPIO0),
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AS3722_PINGROUP(gpio1, GPIO1),
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AS3722_PINGROUP(gpio2, GPIO2),
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AS3722_PINGROUP(gpio3, GPIO3),
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AS3722_PINGROUP(gpio4, GPIO4),
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AS3722_PINGROUP(gpio5, GPIO5),
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AS3722_PINGROUP(gpio6, GPIO6),
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AS3722_PINGROUP(gpio7, GPIO7),
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};
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static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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return as_pci->num_pin_groups;
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}
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static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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return as_pci->pin_groups[group].name;
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}
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static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group, const unsigned **pins, unsigned *num_pins)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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*pins = as_pci->pin_groups[group].pins;
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*num_pins = as_pci->pin_groups[group].npins;
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return 0;
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}
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static const struct pinctrl_ops as3722_pinctrl_ops = {
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.get_groups_count = as3722_pinctrl_get_groups_count,
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.get_group_name = as3722_pinctrl_get_group_name,
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.get_group_pins = as3722_pinctrl_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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return as_pci->num_functions;
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}
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static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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return as_pci->functions[function].name;
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}
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static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function, const char * const **groups,
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unsigned * const num_groups)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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*groups = as_pci->functions[function].groups;
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*num_groups = as_pci->functions[function].ngroups;
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return 0;
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}
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static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
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unsigned group)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
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u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
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int ret;
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dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
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__func__, group, function, val);
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ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
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AS3722_GPIO_IOSF_MASK, val);
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if (ret < 0) {
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dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
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group, ret);
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return ret;
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}
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as_pci->gpio_control[group].io_function = function;
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switch (val) {
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case AS3722_GPIO_IOSF_SD0_OUT:
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case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
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case AS3722_GPIO_IOSF_Q32K_OUT:
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case AS3722_GPIO_IOSF_PWM_OUT:
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case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
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ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
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AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
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if (ret < 0) {
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dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
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group, ret);
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return ret;
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}
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as_pci->gpio_control[group].mode_prop =
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AS3722_GPIO_MODE_OUTPUT_VDDH;
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break;
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default:
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break;
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}
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return ret;
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}
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static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
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{
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if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
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return -EINVAL;
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if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
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if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
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return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
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return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
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}
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if (input) {
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if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
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return AS3722_GPIO_MODE_INPUT_PULL_UP;
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else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
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return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
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return AS3722_GPIO_MODE_INPUT;
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}
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if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
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return AS3722_GPIO_MODE_OUTPUT_VDDL;
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return AS3722_GPIO_MODE_OUTPUT_VDDH;
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}
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static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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if (as_pci->gpio_control[offset].io_function)
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return -EBUSY;
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return 0;
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}
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static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset, bool input)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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struct as3722 *as3722 = as_pci->as3722;
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int mode;
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mode = as3722_pinctrl_gpio_get_mode(
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as_pci->gpio_control[offset].mode_prop, input);
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if (mode < 0) {
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dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
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(input) ? "Input" : "Output", offset);
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return mode;
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}
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return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
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AS3722_GPIO_MODE_MASK, mode);
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}
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static const struct pinmux_ops as3722_pinmux_ops = {
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.get_functions_count = as3722_pinctrl_get_funcs_count,
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.get_function_name = as3722_pinctrl_get_func_name,
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.get_function_groups = as3722_pinctrl_get_func_groups,
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.set_mux = as3722_pinctrl_set,
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.gpio_request_enable = as3722_pinctrl_gpio_request_enable,
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.gpio_set_direction = as3722_pinctrl_gpio_set_direction,
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};
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static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long *config)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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int arg = 0;
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u16 prop;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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prop = AS3722_GPIO_MODE_PULL_UP |
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AS3722_GPIO_MODE_PULL_DOWN;
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if (!(as_pci->gpio_control[pin].mode_prop & prop))
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arg = 1;
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prop = 0;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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prop = AS3722_GPIO_MODE_PULL_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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prop = AS3722_GPIO_MODE_PULL_DOWN;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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prop = AS3722_GPIO_MODE_OPEN_DRAIN;
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break;
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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prop = AS3722_GPIO_MODE_HIGH_IMPED;
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break;
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default:
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dev_err(as_pci->dev, "Properties not supported\n");
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return -ENOTSUPP;
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}
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if (as_pci->gpio_control[pin].mode_prop & prop)
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arg = 1;
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*config = pinconf_to_config_packed(param, (u16)arg);
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return 0;
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}
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static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long *configs,
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unsigned num_configs)
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{
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struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param;
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int mode_prop;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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mode_prop = as_pci->gpio_control[pin].mode_prop;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
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AS3722_GPIO_MODE_PULL_DOWN);
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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mode_prop |= AS3722_GPIO_MODE_PULL_UP;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
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break;
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default:
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dev_err(as_pci->dev, "Properties not supported\n");
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return -ENOTSUPP;
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}
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as_pci->gpio_control[pin].mode_prop = mode_prop;
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}
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return 0;
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}
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static const struct pinconf_ops as3722_pinconf_ops = {
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.pin_config_get = as3722_pinconf_get,
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.pin_config_set = as3722_pinconf_set,
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};
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static struct pinctrl_desc as3722_pinctrl_desc = {
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.pctlops = &as3722_pinctrl_ops,
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.pmxops = &as3722_pinmux_ops,
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.confops = &as3722_pinconf_ops,
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.owner = THIS_MODULE,
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};
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static inline struct as3722_pctrl_info *to_as_pci(struct gpio_chip *chip)
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{
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return container_of(chip, struct as3722_pctrl_info, gpio_chip);
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}
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static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct as3722_pctrl_info *as_pci = to_as_pci(chip);
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struct as3722 *as3722 = as_pci->as3722;
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int ret;
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u32 reg;
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u32 control;
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u32 val;
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int mode;
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int invert_enable;
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ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
|
|
if (ret < 0) {
|
|
dev_err(as_pci->dev,
|
|
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
|
|
return ret;
|
|
}
|
|
|
|
invert_enable = !!(control & AS3722_GPIO_INV);
|
|
mode = control & AS3722_GPIO_MODE_MASK;
|
|
switch (mode) {
|
|
case AS3722_GPIO_MODE_INPUT:
|
|
case AS3722_GPIO_MODE_INPUT_PULL_UP:
|
|
case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
|
|
case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
|
|
case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
|
|
reg = AS3722_GPIO_SIGNAL_IN_REG;
|
|
break;
|
|
case AS3722_GPIO_MODE_OUTPUT_VDDH:
|
|
case AS3722_GPIO_MODE_OUTPUT_VDDL:
|
|
reg = AS3722_GPIO_SIGNAL_OUT_REG;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = as3722_read(as3722, reg, &val);
|
|
if (ret < 0) {
|
|
dev_err(as_pci->dev,
|
|
"GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
val = !!(val & AS3722_GPIOn_SIGNAL(offset));
|
|
return (invert_enable) ? !val : val;
|
|
}
|
|
|
|
static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
|
|
int value)
|
|
{
|
|
struct as3722_pctrl_info *as_pci = to_as_pci(chip);
|
|
struct as3722 *as3722 = as_pci->as3722;
|
|
int en_invert;
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
|
|
if (ret < 0) {
|
|
dev_err(as_pci->dev,
|
|
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
|
|
return;
|
|
}
|
|
en_invert = !!(val & AS3722_GPIO_INV);
|
|
|
|
if (value)
|
|
val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
|
|
else
|
|
val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
|
|
|
|
ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
|
|
AS3722_GPIOn_SIGNAL(offset), val);
|
|
if (ret < 0)
|
|
dev_err(as_pci->dev,
|
|
"GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
|
|
}
|
|
|
|
static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return pinctrl_gpio_direction_input(chip->base + offset);
|
|
}
|
|
|
|
static int as3722_gpio_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
as3722_gpio_set(chip, offset, value);
|
|
return pinctrl_gpio_direction_output(chip->base + offset);
|
|
}
|
|
|
|
static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct as3722_pctrl_info *as_pci = to_as_pci(chip);
|
|
|
|
return as3722_irq_get_virq(as_pci->as3722, offset);
|
|
}
|
|
|
|
static int as3722_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return pinctrl_request_gpio(chip->base + offset);
|
|
}
|
|
|
|
static void as3722_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
pinctrl_free_gpio(chip->base + offset);
|
|
}
|
|
|
|
static const struct gpio_chip as3722_gpio_chip = {
|
|
.label = "as3722-gpio",
|
|
.owner = THIS_MODULE,
|
|
.request = as3722_gpio_request,
|
|
.free = as3722_gpio_free,
|
|
.get = as3722_gpio_get,
|
|
.set = as3722_gpio_set,
|
|
.direction_input = as3722_gpio_direction_input,
|
|
.direction_output = as3722_gpio_direction_output,
|
|
.to_irq = as3722_gpio_to_irq,
|
|
.can_sleep = true,
|
|
.ngpio = AS3722_PIN_NUM,
|
|
.base = -1,
|
|
};
|
|
|
|
static int as3722_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct as3722_pctrl_info *as_pci;
|
|
int ret;
|
|
|
|
as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
|
|
if (!as_pci)
|
|
return -ENOMEM;
|
|
|
|
as_pci->dev = &pdev->dev;
|
|
as_pci->dev->of_node = pdev->dev.parent->of_node;
|
|
as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
|
|
platform_set_drvdata(pdev, as_pci);
|
|
|
|
as_pci->pins = as3722_pins_desc;
|
|
as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
|
|
as_pci->functions = as3722_pin_function;
|
|
as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
|
|
as_pci->pin_groups = as3722_pingroups;
|
|
as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
|
|
as3722_pinctrl_desc.name = dev_name(&pdev->dev);
|
|
as3722_pinctrl_desc.pins = as3722_pins_desc;
|
|
as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
|
|
as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc,
|
|
&pdev->dev, as_pci);
|
|
if (!as_pci->pctl) {
|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
as_pci->gpio_chip = as3722_gpio_chip;
|
|
as_pci->gpio_chip.dev = &pdev->dev;
|
|
as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
|
|
ret = gpiochip_add(&as_pci->gpio_chip);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
|
|
goto fail_chip_add;
|
|
}
|
|
|
|
ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
|
|
0, 0, AS3722_PIN_NUM);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
|
|
goto fail_range_add;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_range_add:
|
|
gpiochip_remove(&as_pci->gpio_chip);
|
|
fail_chip_add:
|
|
pinctrl_unregister(as_pci->pctl);
|
|
return ret;
|
|
}
|
|
|
|
static int as3722_pinctrl_remove(struct platform_device *pdev)
|
|
{
|
|
struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
|
|
|
|
gpiochip_remove(&as_pci->gpio_chip);
|
|
pinctrl_unregister(as_pci->pctl);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id as3722_pinctrl_of_match[] = {
|
|
{ .compatible = "ams,as3722-pinctrl", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
|
|
|
|
static struct platform_driver as3722_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "as3722-pinctrl",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = as3722_pinctrl_of_match,
|
|
},
|
|
.probe = as3722_pinctrl_probe,
|
|
.remove = as3722_pinctrl_remove,
|
|
};
|
|
module_platform_driver(as3722_pinctrl_driver);
|
|
|
|
MODULE_ALIAS("platform:as3722-pinctrl");
|
|
MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
|
|
MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
|
|
MODULE_LICENSE("GPL v2");
|