661 lines
21 KiB
C
661 lines
21 KiB
C
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* I2C controller driver for Qualcomm Technologies Inc platforms
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*/
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#ifndef _I2C_MSM_V2_H
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#define _I2C_MSM_V2_H
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#include <linux/bitops.h>
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#include <linux/dmaengine.h>
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enum msm_i2_debug_level {
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MSM_ERR, /* Error messages only. Always on */
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MSM_PROF, /* High level events. Use for profiling */
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MSM_DBG, /* Low level details. Use for debugging */
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};
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#define i2c_msm_dbg(ctrl, dbg_level, fmt, ...) do {\
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if (ctrl->dbgfs.dbg_lvl >= dbg_level)\
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dev_info(ctrl->dev, pr_fmt(fmt), ##__VA_ARGS__);\
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} while (0)
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#define BIT_IS_SET(val, idx) ((val >> idx) & 0x1)
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#define BITS_AT(val, idx, n_bits)(((val) & (((1 << n_bits) - 1) << idx)) >> idx)
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#define MASK_IS_SET(val, mask) ((val & mask) == mask)
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#define MASK_IS_SET_BOOL(val, mask) (MASK_IS_SET(val, mask) ? 1 : 0)
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#define KHz(freq) (1000 * freq)
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#define I2C_MSM_CLK_FAST_PLUS_FREQ (1000000)
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/* QUP Registers */
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enum {
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QUP_CONFIG = 0x0,
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QUP_STATE = 0x4,
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QUP_IO_MODES = 0x8,
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QUP_SW_RESET = 0xC,
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QUP_OPERATIONAL = 0x18,
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QUP_ERROR_FLAGS = 0x1C,
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QUP_ERROR_FLAGS_EN = 0x20,
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QUP_TEST_CTRL = 0x24,
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QUP_OPERATIONAL_MASK = 0x28,
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QUP_HW_VERSION = 0x30,
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QUP_MX_READ_COUNT = 0x208,
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QUP_MX_WRITE_COUNT = 0x150,
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QUP_MX_OUTPUT_COUNT = 0x100,
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QUP_MX_INPUT_COUNT = 0x200,
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QUP_MX_WR_CNT = 0x100,
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QUP_OUT_DEBUG = 0x108,
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QUP_OUT_FIFO_CNT = 0x10C,
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QUP_OUT_FIFO_BASE = 0x110,
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QUP_IN_READ_CUR = 0x20C,
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QUP_IN_DEBUG = 0x210,
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QUP_IN_FIFO_CNT = 0x214,
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QUP_IN_FIFO_BASE = 0x218,
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QUP_I2C_MASTER_CLK_CTL = 0x400,
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QUP_I2C_STATUS = 0x404,
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QUP_I2C_MASTER_CONFIG = 0x408,
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QUP_I2C_MASTER_BUS_CLR = 0x40C,
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};
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/* Register:QUP_STATE state field values */
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enum i2c_msm_qup_state {
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QUP_STATE_RESET = 0,
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QUP_STATE_RUN = 1U,
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QUP_STATE_PAUSE = 3U,
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};
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/* Register:QUP_STATE fields */
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enum {
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QUP_STATE_MASK = 3U,
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QUP_STATE_VALID = BIT(2),
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QUP_I2C_MAST_GEN = BIT(4),
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QUP_I2C_FLUSH = BIT(6),
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QUP_I2C_STATUS_RESET = 0x42,
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};
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/* Register:QUP_CONFIG fields */
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enum {
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QUP_MINI_CORE_MASK = 0xF00,
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QUP_MINI_CORE_I2C_VAL = 0x200,
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QUP_N_MASK = 0x1F,
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QUP_N_VAL = 0x7, /* 0xF for A family */
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QUP_NO_OUPUT = BIT(6),
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QUP_NO_INPUT = BIT(7),
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QUP_APP_CLK_ON_EN = BIT(12),
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QUP_CORE_CLK_ON_EN = BIT(13),
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QUP_FIFO_CLK_GATE_EN = BIT(14),
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};
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/* Register:QUP_OPERATIONAL fields */
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enum {
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QUP_INPUT_FIFO_NOT_EMPTY = BIT(5),
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QUP_OUTPUT_SERVICE_FLAG = BIT(8),
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QUP_INPUT_SERVICE_FLAG = BIT(9),
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QUP_MAX_OUTPUT_DONE_FLAG = BIT(10),
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QUP_MAX_INPUT_DONE_FLAG = BIT(11),
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QUP_OUT_BLOCK_WRITE_REQ = BIT(12),
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QUP_IN_BLOCK_READ_REQ = BIT(13),
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};
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/* Register:QUP_OPERATIONAL_MASK fields */
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enum {
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QUP_INPUT_SERVICE_MASK = BIT(9),
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QUP_OUTPUT_SERVICE_MASK = BIT(8),
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};
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/* Register:QUP_IO_MODES fields */
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enum {
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QUP_OUTPUT_MODE = BIT(10) | BIT(11),
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QUP_INPUT_MODE = BIT(12) | BIT(13),
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QUP_UNPACK_EN = BIT(14),
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QUP_PACK_EN = BIT(15),
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QUP_OUTPUT_BIT_SHIFT_EN = BIT(16),
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};
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/* Register:QUP_I2C_STATUS (a.k.a I2C_MASTER_STATUS) fields */
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enum {
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QUP_BUS_ERROR = BIT(2),
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QUP_PACKET_NACKED = BIT(3),
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QUP_ARB_LOST = BIT(4),
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QUP_INVALID_WRITE = BIT(5),
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QUP_FAILED = BIT(6),
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QUP_BUS_ACTIVE = BIT(8),
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QUP_BUS_MASTER = BIT(9),
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QUP_INVALID_TAG = BIT(23),
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QUP_INVALID_READ_ADDR = BIT(24),
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QUP_INVALID_READ_SEQ = BIT(25),
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QUP_I2C_SDA = BIT(26),
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QUP_I2C_SCL = BIT(27),
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QUP_MSTR_STTS_ERR_MASK = 0x380003C,
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};
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/* Register:QUP_I2C_MASTER_CONFIG fields */
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enum {
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QUP_EN_VERSION_TWO_TAG = 1U,
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};
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/* Register:QUP_I2C_MASTER_CLK_CTL field setters */
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#define I2C_MSM_SCL_NOISE_REJECTION(reg_val, noise_rej_val) \
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(((reg_val) & ~(0x3 << 24)) | (((noise_rej_val) & 0x3) << 24))
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#define I2C_MSM_SDA_NOISE_REJECTION(reg_val, noise_rej_val) \
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(((reg_val) & ~(0x3 << 26)) | (((noise_rej_val) & 0x3) << 26))
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/* Register:QUP_ERROR_FLAGS_EN flags */
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enum {
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QUP_OUTPUT_OVER_RUN_ERR_EN = BIT(5),
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QUP_INPUT_UNDER_RUN_ERR_EN = BIT(4),
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QUP_OUTPUT_UNDER_RUN_ERR_EN = BIT(3),
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QUP_INPUT_OVER_RUN_ERR_EN = BIT(2),
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};
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/* Status, Error flags */
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enum {
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I2C_STATUS_WR_BUFFER_FULL = BIT(0),
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I2C_STATUS_BUS_ACTIVE = BIT(8),
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I2C_STATUS_BUS_MASTER = BIT(9),
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I2C_STATUS_ERROR_MASK = 0x38000FC,
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QUP_I2C_NACK_FLAG = BIT(3),
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QUP_IN_NOT_EMPTY = BIT(5),
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QUP_ERR_FLGS_MASK = 0x3C,
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};
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/* Master status clock states */
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enum {
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I2C_CLK_RESET_BUSIDLE_STATE = 0,
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I2C_CLK_FORCED_LOW_STATE = 5,
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};
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/* Controller's power state */
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enum i2c_msm_power_state {
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I2C_MSM_PM_RT_ACTIVE,
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I2C_MSM_PM_RT_SUSPENDED,
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I2C_MSM_PM_SYS_SUSPENDED
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};
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/*
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* The max buffer size required for tags is for holding the following sequence:
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* [start] + [start | slv-addr] + [ rd/wr | len]
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* which sum up to 6 bytes. However, we use u64 to hold the value, thus we say
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* that max length is 8 bytes.
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*/
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#define I2C_MSM_TAG2_MAX_LEN (4)
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#define I2C_MSM_DMA_TX_SZ (64) /* tx chan n entries */
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#define I2C_MSM_DMA_RX_SZ (32) /* rx chan n entries */
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#define I2C_MSM_DMA_DESC_ARR_SIZ (I2C_MSM_DMA_TX_SZ + I2C_MSM_DMA_RX_SZ)
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#define I2C_MSM_REG_2_STR_BUF_SZ (128)
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/* Optimal value to hold the error strings */
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#define I2C_MSM_MAX_ERR_BUF_SZ (256)
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#define I2C_MSM_BUF_DUMP_MAX_BC (20)
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#define I2C_MSM_MAX_POLL_MSEC (100)
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#define I2C_MSM_TIMEOUT_SAFTY_COEF (10)
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#define I2C_MSM_TIMEOUT_MIN_USEC (500000)
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#define I2C_QUP_MAX_BUS_RECOVERY_RETRY (10)
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/* QUP v2 tags */
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#define QUP_TAG2_DATA_WRITE (0x82ULL)
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#define QUP_TAG2_DATA_WRITE_N_STOP (0x83ULL)
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#define QUP_TAG2_DATA_READ (0x85ULL)
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#define QUP_TAG2_DATA_READ_N_STOP (0x87ULL)
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#define QUP_TAG2_START (0x81ULL)
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#define QUP_TAG2_DATA_READ_N_NACK (0x86ULL)
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#define QUP_TAG2_START_STOP (0x8AULL)
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#define QUP_TAG2_INPUT_EOT (0x93ULL)
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#define QUP_TAG2_FLUSH_STOP (0x96ULL)
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#define QUP_BUF_OVERHD_BC (2)
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#define QUP_MAX_BUF_SZ (256)
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enum i2c_msm_clk_path_vec_idx {
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I2C_MSM_CLK_PATH_SUSPEND_VEC,
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I2C_MSM_CLK_PATH_RESUME_VEC,
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};
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#define I2C_MSM_CLK_PATH_AVRG_BW(ctrl) (0)
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#define I2C_MSM_CLK_PATH_BRST_BW(ctrl) (ctrl->rsrcs.clk_freq_in * 8)
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enum i2c_msm_gpio_name_idx {
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I2C_MSM_GPIO_SCL,
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I2C_MSM_GPIO_SDA,
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};
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extern const char * const i2c_msm_mode_str_tbl[];
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struct i2c_msm_ctrl;
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/*
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* i2c_msm_dma_mem: utility struct which holds both physical and virtual addr
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*/
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struct i2c_msm_dma_mem {
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dma_addr_t phy_addr;
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void *vrtl_addr;
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};
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/*
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* i2c_msm_tag: tag's data and its length.
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*
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* @len tag len can be two, four or six bytes.
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*/
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struct i2c_msm_tag {
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u64 val;
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int len;
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};
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/*
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* i2c_msm_dma_tag: similar to struct i2c_msm_tag but holds physical address.
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*
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* @buf physical address of entry in the tag_arr of
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* struct i2c_msm_xfer_mode_dma
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* @len tag len.
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*
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* Hold the information from i2c_msm_dma_xfer_prepare() which is used by
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* i2c_msm_dma_xfer_process() and freed by i2c_msm_dma_xfer_unprepare()
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*/
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struct i2c_msm_dma_tag {
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dma_addr_t buf;
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size_t len;
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};
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/*
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* i2c_msm_dma_buf: dma mapped pointer to i2c_msg data buffer and related tag
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* @vir_addr ptr to i2c_msg buf beginning or with offset (when buf len > 256)
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*/
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struct i2c_msm_dma_buf {
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struct i2c_msm_dma_mem ptr;
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enum dma_data_direction dma_dir;
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size_t len;
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bool is_rx;
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bool is_last;
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struct i2c_msm_dma_tag tag;
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/* DMA API */
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struct scatterlist sg_list[2];
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};
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/*
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* i2c_msm_dma_chan: per channel info
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*
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* @is_init true when the channel is initialized and requires eventual teardown.
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* @name channel name (tx/rx) for debugging.
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* @desc_cnt_cur number of occupied descriptors
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*/
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struct i2c_msm_dma_chan {
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bool is_init;
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const char *name;
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size_t desc_cnt_cur;
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struct dma_chan *dma_chan;
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enum dma_transfer_direction dir;
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};
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enum i2c_msm_dma_chan_dir {
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I2C_MSM_DMA_TX,
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I2C_MSM_DMA_RX,
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I2C_MSM_DMA_CNT,
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};
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enum i2c_msm_dma_state {
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I2C_MSM_DMA_INIT_NONE, /* Uninitialized DMA */
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I2C_MSM_DMA_INIT_CORE, /* Core init not channels, memory Allocated */
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I2C_MSM_DMA_INIT_CHAN, /* Both Core and channels are init */
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};
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/*
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* struct i2c_msm_xfer_mode_dma: DMA mode configuration and work space
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*
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* @state specifies the DMA core and channel initialization states.
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* @buf_arr_cnt current number of valid buffers in buf_arr. The valid buffers
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* are at index 0..buf_arr_cnt excluding buf_arr_cnt.
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* @buf_arr array of descriptors which point to the user's buffer
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* virtual and physical address, and hold meta data about the buffer
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* and respective tag.
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* @tag_arr array of tags in DMAable memory. Holds a tag per buffer of the same
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* index, that is tag_arr[i] is related to buf_arr[i]. Also, tag_arr[i]
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* is queued in the tx channel just befor buf_arr[i] is queued in
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* the tx (output buf) or rx channel (input buffer).
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* @eot_n_flush_stop_tags EOT and flush-stop tags to be queued to the tx
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* DMA channel after the last transfer when it is a read.
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* @input_tag hw is placing input tags in the rx channel on read operations.
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* The value of these tags is "don't care" from DMA transfer
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* perspective. Thus, this single buffer is used for all the input
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* tags. The field is used as write only.
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*/
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struct i2c_msm_xfer_mode_dma {
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enum i2c_msm_dma_state state;
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size_t buf_arr_cnt;
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struct i2c_msm_dma_buf buf_arr[I2C_MSM_DMA_DESC_ARR_SIZ];
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struct i2c_msm_dma_mem tag_arr;
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struct i2c_msm_dma_mem eot_n_flush_stop_tags;
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struct i2c_msm_dma_mem input_tag;
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struct i2c_msm_dma_chan chan[I2C_MSM_DMA_CNT];
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};
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/*
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* I2C_MSM_DMA_TAG_MEM_SZ includes the following fields of
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* struct i2c_msm_xfer_mode_dma (in order):
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*
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* Buffer of DMA memory:
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* +-----------+---------+-----------+-----------+----+-----------+
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* | input_tag | eot_... | tag_arr 0 | tag_arr 1 | .. | tag_arr n |
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* +-----------+---------+-----------+-----------+----+-----------+
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*
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* Why +2?
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* One tag buffer for the input tags. This is a write only buffer for DMA, it is
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* used to read the tags of the input fifo. We let them overwrite each other,
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* since it is a throw-away from the driver's perspective.
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* Second tag buffer for the EOT and flush-stop tags. This is a read only
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* buffer (from DMA perspective). It is used to put EOT and flush-stop at the
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* end of every transaction.
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*/
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#define I2C_MSM_DMA_TAG_MEM_SZ \
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((I2C_MSM_DMA_DESC_ARR_SIZ + 2) * I2C_MSM_TAG2_MAX_LEN)
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/*
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* i2c_msm_xfer_mode_fifo: operations and state of FIFO mode
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*
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* @ops "base class" of i2c_msm_xfer_mode_dma. Contains the operations while
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* the rest of the fields contain the data.
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* @input_fifo_sz input fifo size in bytes
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* @output_fifo_sz output fifo size in bytes
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* @in_rem remaining u32 entries in input FIFO before empty
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* @out_rem remaining u32 entries in output FIFO before full
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* @out_buf buffer for collecting bytes to four bytes groups (u32) before
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* writing them to the output fifo.
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* @out_buf_idx next free index in out_buf. 0..3
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*/
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struct i2c_msm_xfer_mode_fifo {
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size_t input_fifo_sz;
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size_t output_fifo_sz;
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size_t in_rem;
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size_t out_rem;
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u8 out_buf[4];
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int out_buf_idx;
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};
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/* i2c_msm_xfer_mode_blk: operations and state of Block mode
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*
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* @is_init when true, struct is initialized and requires mem free on exit
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* @in_blk_sz size of input/rx block
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* @out_blk_sz size of output/tx block
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* @tx_cache internal buffer to store tx data
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* @rx_cache internal buffer to store rx data
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* @rx_cache_idx points to the next unread index in rx cache
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* @tx_cache_idx points to the next unwritten index in tx cache
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* @wait_rx_blk completion object to wait on for end of blk rx transfer.
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* @wait_tx_blk completion object to wait on for end of blk tx transfer.
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* @complete_mask applied to QUP_OPERATIONAL to determine when blk
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* xfer is complete.
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*/
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struct i2c_msm_xfer_mode_blk {
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bool is_init;
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size_t in_blk_sz;
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size_t out_blk_sz;
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u8 *tx_cache;
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u8 *rx_cache;
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int rx_cache_idx;
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int tx_cache_idx;
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struct completion wait_rx_blk;
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struct completion wait_tx_blk;
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u32 complete_mask;
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};
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/* INPUT_MODE and OUTPUT_MODE filds of QUP_IO_MODES register */
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enum i2c_msm_xfer_mode_id {
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I2C_MSM_XFER_MODE_FIFO,
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I2C_MSM_XFER_MODE_BLOCK,
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I2C_MSM_XFER_MODE_DMA,
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I2C_MSM_XFER_MODE_NONE, /* keep last as a counter */
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};
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struct i2c_msm_dbgfs {
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struct dentry *root;
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enum msm_i2_debug_level dbg_lvl;
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enum i2c_msm_xfer_mode_id force_xfer_mode;
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};
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/*
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* qup_i2c_clk_path_vote: data to use bus scaling driver for clock path vote
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*
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* @mstr_id master id number of the i2c core or its wrapper (BLSP/GSBI).
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* When zero, clock path voting is disabled.
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* @client_hdl when zero, client is not registered with the bus scaling driver,
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* and bus scaling functionality should not be used. When non zero, it
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* is a bus scaling client id and may be used to vote for clock path.
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* @reg_err when true, registration error was detected and an error message was
|
|
* logged. i2c will attempt to re-register but will log error only once.
|
|
* once registration succeed, the flag is set to false.
|
|
* @actv_only when set, votes when system active and removes the vote when
|
|
* system goes idle (optimises for performance). When unset, voting using
|
|
* runtime pm (optimizes for power).
|
|
*/
|
|
struct qup_i2c_clk_path_vote {
|
|
u32 mstr_id;
|
|
u32 client_hdl;
|
|
struct msm_bus_scale_pdata *pdata;
|
|
bool reg_err;
|
|
bool actv_only;
|
|
};
|
|
|
|
/*
|
|
* i2c_msm_resources: OS resources
|
|
*
|
|
* @mem I2C controller memory resource from platform data.
|
|
* @base I2C controller virtual base address
|
|
* @clk_freq_in core clock frequency in Hz
|
|
* @clk_freq_out bus clock frequency in Hz
|
|
*/
|
|
struct i2c_msm_resources {
|
|
struct resource *mem;
|
|
void __iomem *base; /* virtual */
|
|
struct clk *core_clk;
|
|
struct clk *iface_clk;
|
|
int clk_freq_in;
|
|
int clk_freq_out;
|
|
struct qup_i2c_clk_path_vote clk_path_vote;
|
|
int irq;
|
|
bool disable_dma;
|
|
struct pinctrl *pinctrl;
|
|
struct pinctrl_state *gpio_state_active;
|
|
struct pinctrl_state *gpio_state_suspend;
|
|
};
|
|
|
|
#define I2C_MSM_PINCTRL_ACTIVE "i2c_active"
|
|
#define I2C_MSM_PINCTRL_SUSPEND "i2c_sleep"
|
|
|
|
/*
|
|
* i2c_msm_xfer_buf: current xfer position and preprocessed tags
|
|
*
|
|
* @is_init the buf is marked initialized by the first call to
|
|
* i2c_msm_xfer_next_buf()
|
|
* @msg_idx index of the message that the buffer is pointing to
|
|
* @byte_idx index of first byte in the current buffer
|
|
* @end_idx count of bytes processed from the current message. This value
|
|
* is compared against len to find out if buffer is done processing.
|
|
* @len number of bytes in current buffer.
|
|
* @is_rx when true, current buffer is pointing to a i2c read operation.
|
|
* @slv_addr 8 bit address. This is the i2c_msg->addr + rd/wr bit.
|
|
*
|
|
* Keep track of current position in the client's transfer request and
|
|
* pre-process a transfer's buffer and tags.
|
|
*/
|
|
struct i2c_msm_xfer_buf {
|
|
bool is_init;
|
|
int msg_idx;
|
|
int byte_idx;
|
|
int end_idx;
|
|
int len;
|
|
bool is_rx;
|
|
bool is_last;
|
|
u16 slv_addr;
|
|
struct i2c_msm_tag in_tag;
|
|
struct i2c_msm_tag out_tag;
|
|
};
|
|
|
|
#ifdef DEBUG
|
|
#define I2C_MSM_PROF_MAX_EVNTS (64)
|
|
#else
|
|
#define I2C_MSM_PROF_MAX_EVNTS (16)
|
|
#endif
|
|
|
|
/*
|
|
* i2c_msm_prof_event: profiling event
|
|
*
|
|
* @data Additional data about the event. The interpretation of the data is
|
|
* dependant on the type field.
|
|
* @type event type (see enum i2c_msm_prof_event_type)
|
|
*/
|
|
struct i2c_msm_prof_event {
|
|
struct timespec time;
|
|
u64 data0;
|
|
u32 data1;
|
|
u32 data2;
|
|
u8 type;
|
|
u8 dump_func_id;
|
|
};
|
|
|
|
enum i2c_msm_err {
|
|
I2C_MSM_NO_ERR = 0,
|
|
I2C_MSM_ERR_NACK,
|
|
I2C_MSM_ERR_ARB_LOST,
|
|
I2C_MSM_ERR_BUS_ERR,
|
|
I2C_MSM_ERR_TIMEOUT,
|
|
I2C_MSM_ERR_CORE_CLK,
|
|
I2C_MSM_ERR_OVR_UNDR_RUN,
|
|
};
|
|
|
|
/*
|
|
* i2c_msm_xfer: A client transfer request. A list of one or more i2c messages
|
|
*
|
|
* @msgs NULL when no active xfer. Points to array of i2c_msgs
|
|
* given by the client.
|
|
* @msg_cnt number of messages in msgs array.
|
|
* @complete completion object to wait on for end of transfer.
|
|
* @rx_cnt number of input bytes in the client's request.
|
|
* @tx_cnt number of output bytes in the client's request.
|
|
* @rx_ovrhd_cnt number of input bytes due to tags.
|
|
* @tx_ovrhd_cnt number of output bytes due to tags.
|
|
* @event profiling data. An array of timestamps of transfer events
|
|
* @event_cnt number of items in event array.
|
|
* @is_active true during xfer process and false after xfer end
|
|
* @mtx mutex to solve multithreaded problem in xfer
|
|
*/
|
|
struct i2c_msm_xfer {
|
|
struct i2c_msg *msgs;
|
|
int msg_cnt;
|
|
enum i2c_msm_xfer_mode_id mode_id;
|
|
struct completion complete;
|
|
size_t rx_cnt;
|
|
size_t tx_cnt;
|
|
size_t rx_ovrhd_cnt;
|
|
size_t tx_ovrhd_cnt;
|
|
struct i2c_msm_xfer_buf cur_buf;
|
|
u32 timeout;
|
|
bool last_is_rx;
|
|
enum i2c_msm_err err;
|
|
struct i2c_msm_prof_event event[I2C_MSM_PROF_MAX_EVNTS];
|
|
atomic_t event_cnt;
|
|
atomic_t is_active;
|
|
struct mutex mtx;
|
|
struct i2c_msm_xfer_mode_fifo fifo;
|
|
struct i2c_msm_xfer_mode_blk blk;
|
|
struct i2c_msm_xfer_mode_dma dma;
|
|
};
|
|
|
|
/*
|
|
* i2c_msm_ctrl: the driver's main struct
|
|
*
|
|
* @is_init true when
|
|
* @ver info that is different between i2c controller versions
|
|
* @ver_num ha
|
|
* @xfer state of the currently processed transfer.
|
|
* @dbgfs debug-fs root and values that may be set via debug-fs.
|
|
* @rsrcs resources from platform data including clocks, gpios, irqs, and
|
|
* memory regions.
|
|
* @mstr_clk_ctl cached value for programming to mstr_clk_ctl register
|
|
*/
|
|
struct i2c_msm_ctrl {
|
|
struct device *dev;
|
|
struct i2c_adapter adapter;
|
|
struct i2c_msm_xfer xfer;
|
|
struct i2c_msm_dbgfs dbgfs;
|
|
struct i2c_msm_resources rsrcs;
|
|
u32 mstr_clk_ctl;
|
|
enum i2c_msm_power_state pwr_state;
|
|
};
|
|
|
|
/* Enum for the profiling event types */
|
|
enum i2c_msm_prof_evnt_type {
|
|
I2C_MSM_VALID_END,
|
|
I2C_MSM_PIP_DSCN,
|
|
I2C_MSM_PIP_CNCT,
|
|
I2C_MSM_ACTV_END,
|
|
I2C_MSM_IRQ_BGN,
|
|
I2C_MSM_IRQ_END,
|
|
I2C_MSM_XFER_BEG,
|
|
I2C_MSM_XFER_END,
|
|
I2C_MSM_SCAN_SUM,
|
|
I2C_MSM_NEXT_BUF,
|
|
I2C_MSM_COMPLT_OK,
|
|
I2C_MSM_COMPLT_FL,
|
|
I2C_MSM_PROF_RESET,
|
|
};
|
|
|
|
#ifdef CONFIG_I2C_MSM_PROF_DBG
|
|
void i2c_msm_dbgfs_init(struct i2c_msm_ctrl *ctrl);
|
|
|
|
void i2c_msm_dbgfs_teardown(struct i2c_msm_ctrl *ctrl);
|
|
|
|
/* diagonisis the i2c registers and dump the errors accordingly */
|
|
const char *i2c_msm_dbg_tag_to_str(const struct i2c_msm_tag *tag,
|
|
char *buf, size_t buf_len);
|
|
|
|
void i2c_msm_prof_evnt_dump(struct i2c_msm_ctrl *ctrl);
|
|
|
|
/* function definitions to be used from the i2c-msm-v2-debug file */
|
|
void i2c_msm_prof_evnt_add(struct i2c_msm_ctrl *ctrl,
|
|
enum msm_i2_debug_level dbg_level,
|
|
enum i2c_msm_prof_evnt_type event,
|
|
u64 data0, u32 data1, u32 data2);
|
|
|
|
int i2c_msm_dbg_qup_reg_dump(struct i2c_msm_ctrl *ctrl);
|
|
|
|
const char *
|
|
i2c_msm_dbg_dma_tag_to_str(const struct i2c_msm_dma_tag *dma_tag, char *buf,
|
|
size_t buf_len);
|
|
#else
|
|
/* use dummy functions */
|
|
static inline void i2c_msm_dbgfs_init(struct i2c_msm_ctrl *ctrl) {}
|
|
static inline void i2c_msm_dbgfs_teardown(struct i2c_msm_ctrl *ctrl) {}
|
|
|
|
static inline const char *i2c_msm_dbg_tag_to_str(const struct i2c_msm_tag *tag,
|
|
char *buf, size_t buf_len)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline void i2c_msm_prof_evnt_dump(struct i2c_msm_ctrl *ctrl) {}
|
|
|
|
/* function definitions to be used from the i2c-msm-v2-debug file */
|
|
static inline void i2c_msm_prof_evnt_add(struct i2c_msm_ctrl *ctrl,
|
|
enum msm_i2_debug_level dbg_level,
|
|
enum i2c_msm_prof_evnt_type event,
|
|
u64 data0, u32 data1, u32 data2) {}
|
|
|
|
static inline int i2c_msm_dbg_qup_reg_dump(struct i2c_msm_ctrl *ctrl)
|
|
{
|
|
return true;
|
|
}
|
|
static inline const char *i2c_msm_dbg_dma_tag_to_str(const struct
|
|
i2c_msm_dma_tag * dma_tag, char *buf, size_t buf_len)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* I2C_MSM_V2_PROF_DBG */
|
|
#endif /* _I2C_MSM_V2_H */
|