679 lines
21 KiB
Text
679 lines
21 KiB
Text
==========================================
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ARM idle states binding description
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==========================================
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==========================================
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1 - Introduction
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==========================================
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ARM systems contain HW capable of managing power consumption dynamically,
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where cores can be put in different low-power states (ranging from simple
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wfi to power gating) according to OS PM policies. The CPU states representing
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the range of dynamic idle states that a processor can enter at run-time, can be
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specified through device tree bindings representing the parameters required
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to enter/exit specific idle states on a given processor.
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According to the Server Base System Architecture document (SBSA, [3]), the
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power states an ARM CPU can be put into are identified by the following list:
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- Running
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- Idle_standby
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- Idle_retention
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- Sleep
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- Off
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The power states described in the SBSA document define the basic CPU states on
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top of which ARM platforms implement power management schemes that allow an OS
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PM implementation to put the processor in different idle states (which include
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states listed above; "off" state is not an idle state since it does not have
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wake-up capabilities, hence it is not considered in this document).
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Idle state parameters (eg entry latency) are platform specific and need to be
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characterized with bindings that provide the required information to OS PM
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code so that it can build the required tables and use them at runtime.
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The device tree binding definition for ARM idle states is the subject of this
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document.
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===========================================
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2 - idle-states definitions
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===========================================
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Idle states are characterized for a specific system through a set of
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timing and energy related properties, that underline the HW behaviour
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triggered upon idle states entry and exit.
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The following diagram depicts the CPU execution phases and related timing
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properties required to enter and exit an idle state:
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..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
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| | | | |
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|<------ entry ------->|
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| latency |
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|<- exit ->|
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| latency |
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|<-------- min-residency -------->|
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|<------- wakeup-latency ------->|
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Diagram 1: CPU idle state execution phases
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EXEC: Normal CPU execution.
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PREP: Preparation phase before committing the hardware to idle mode
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like cache flushing. This is abortable on pending wake-up
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event conditions. The abort latency is assumed to be negligible
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(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
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goes back to EXEC. This phase is optional. If not abortable,
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this should be included in the ENTRY phase instead.
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ENTRY: The hardware is committed to idle mode. This period must run
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to completion up to IDLE before anything else can happen.
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IDLE: This is the actual energy-saving idle period. This may last
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between 0 and infinite time, until a wake-up event occurs.
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EXIT: Period during which the CPU is brought back to operational
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mode (EXEC).
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entry-latency: Worst case latency required to enter the idle state. The
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exit-latency may be guaranteed only after entry-latency has passed.
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min-residency: Minimum period, including preparation and entry, for a given
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idle state to be worthwhile energywise.
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wakeup-latency: Maximum delay between the signaling of a wake-up event and the
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CPU being able to execute normal code again. If not specified, this is assumed
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to be entry-latency + exit-latency.
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These timing parameters can be used by an OS in different circumstances.
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An idle CPU requires the expected min-residency time to select the most
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appropriate idle state based on the expected expiry time of the next IRQ
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(ie wake-up) that causes the CPU to return to the EXEC phase.
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An operating system scheduler may need to compute the shortest wake-up delay
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for CPUs in the system by detecting how long will it take to get a CPU out
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of an idle state, eg:
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wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
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In other words, the scheduler can make its scheduling decision by selecting
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(eg waking-up) the CPU with the shortest wake-up latency.
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The wake-up latency must take into account the entry latency if that period
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has not expired. The abortable nature of the PREP period can be ignored
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if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
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the worst case since it depends on the CPU operating conditions, ie caches
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state).
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An OS has to reliably probe the wakeup-latency since some devices can enforce
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latency constraints guarantees to work properly, so the OS has to detect the
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worst case wake-up latency it can incur if a CPU is allowed to enter an
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idle state, and possibly to prevent that to guarantee reliable device
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functioning.
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The min-residency time parameter deserves further explanation since it is
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expressed in time units but must factor in energy consumption coefficients.
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The energy consumption of a cpu when it enters a power state can be roughly
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characterised by the following graph:
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e |
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n | /---
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e | /------
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r | /------
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g | /-----
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y | /------
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| ----
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| /|
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| / |
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| / |
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| / |
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|/ |
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-----|-------+----------------------------------
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0| 1 time(ms)
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Graph 1: Energy vs time example
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The graph is split in two parts delimited by time 1ms on the X-axis.
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The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
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and denotes the energy costs incurred whilst entering and leaving the idle
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state.
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The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
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shallower slope and essentially represents the energy consumption of the idle
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state.
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min-residency is defined for a given idle state as the minimum expected
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residency time for a state (inclusive of preparation and entry) after
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which choosing that state become the most energy efficient option. A good
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way to visualise this, is by taking the same graph above and comparing some
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states energy consumptions plots.
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For sake of simplicity, let's consider a system with two idle states IDLE1,
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and IDLE2:
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| /-- IDLE1
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e | /---
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n | /----
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e | /---
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r | /-----/--------- IDLE2
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g | /-------/---------
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y | ------------ /---|
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| / /---- |
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| / /--- |
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| / /---- |
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| / /--- |
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| --- |
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| / |
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|/ | time
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---/----------------------------+------------------------
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|IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
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IDLE2-min-residency
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Graph 2: idle states min-residency example
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In graph 2 above, that takes into account idle states entry/exit energy
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costs, it is clear that if the idle state residency time (ie time till next
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wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
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choice energywise.
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This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
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than IDLE2.
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However, the lower power consumption (ie shallower energy curve slope) of idle
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state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
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efficient.
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The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
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shallower states in a system with multiple idle states) is defined
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IDLE2-min-residency and corresponds to the time when energy consumption of
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IDLE1 and IDLE2 states breaks even.
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The definitions provided in this section underpin the idle states
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properties specification that is the subject of the following sections.
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===========================================
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3 - idle-states node
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===========================================
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ARM processor idle states are defined within the idle-states node, which is
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a direct child of the cpus node [1] and provides a container where the
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processor idle states, defined as device tree nodes, are listed.
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- idle-states node
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Usage: Optional - On ARM systems, it is a container of processor idle
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states nodes. If the system does not provide CPU
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power management capabilities or the processor just
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supports idle_standby an idle-states node is not
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required.
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Description: idle-states node is a container node, where its
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subnodes describe the CPU idle states.
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Node name must be "idle-states".
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The idle-states node's parent node must be the cpus node.
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The idle-states node's child nodes can be:
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- one or more state nodes
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Any other configuration is considered invalid.
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An idle-states node defines the following properties:
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- entry-method
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Value type: <stringlist>
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Usage and definition depend on ARM architecture version.
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# On ARM v8 64-bit this property is required and must
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be one of:
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- "psci" (see bindings in [2])
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# On ARM 32-bit systems this property is optional
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The nodes describing the idle states (state) can only be defined within the
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idle-states node, any other configuration is considered invalid and therefore
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must be ignored.
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===========================================
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4 - state node
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===========================================
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A state node represents an idle state description and must be defined as
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follows:
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- state node
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Description: must be child of the idle-states node
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The state node name shall follow standard device tree naming
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rules ([5], 2.2.1 "Node names"), in particular state nodes which
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are siblings within a single common parent must be given a unique name.
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The idle state entered by executing the wfi instruction (idle_standby
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SBSA,[3][4]) is considered standard on all ARM platforms and therefore
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must not be listed.
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With the definitions provided above, the following list represents
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the valid properties for a state node:
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- compatible
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Usage: Required
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Value type: <stringlist>
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Definition: Must be "arm,idle-state".
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- local-timer-stop
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Usage: See definition
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Value type: <none>
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Definition: if present the CPU local timer control logic is
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lost on state entry, otherwise it is retained.
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- entry-latency-us
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: u32 value representing worst case latency in
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microseconds required to enter the idle state.
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The exit-latency-us duration may be guaranteed
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only after entry-latency-us has passed.
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- exit-latency-us
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: u32 value representing worst case latency
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in microseconds required to exit the idle state.
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- min-residency-us
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Usage: Required
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Value type: <prop-encoded-array>
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Definition: u32 value representing minimum residency duration
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in microseconds, inclusive of preparation and
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entry, for this idle state to be considered
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worthwhile energy wise (refer to section 2 of
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this document for a complete description).
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- wakeup-latency-us:
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Usage: Optional
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Value type: <prop-encoded-array>
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Definition: u32 value representing maximum delay between the
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signaling of a wake-up event and the CPU being
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able to execute normal code again. If omitted,
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this is assumed to be equal to:
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entry-latency-us + exit-latency-us
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It is important to supply this value on systems
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where the duration of PREP phase (see diagram 1,
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section 2) is non-neglibigle.
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In such systems entry-latency-us + exit-latency-us
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will exceed wakeup-latency-us by this duration.
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In addition to the properties listed above, a state node may require
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additional properties specifics to the entry-method defined in the
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idle-states node, please refer to the entry-method bindings
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documentation for properties definitions.
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===========================================
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4 - Examples
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===========================================
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Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
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cpus {
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#size-cells = <0>;
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#address-cells = <2>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU5: cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU6: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU7: cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
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};
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CPU8: cpu@100000000 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU9: cpu@100000001 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU10: cpu@100000100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU11: cpu@100000101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU12: cpu@100010000 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x10000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU13: cpu@100010001 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x10001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU14: cpu@100010100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x10100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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CPU15: cpu@100010101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x10101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
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};
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idle-states {
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entry-method = "arm,psci";
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CPU_RETENTION_0_0: cpu-retention-0-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <20>;
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exit-latency-us = <40>;
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min-residency-us = <80>;
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};
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CLUSTER_RETENTION_0: cluster-retention-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <250>;
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wakeup-latency-us = <130>;
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};
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CPU_SLEEP_0_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <250>;
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exit-latency-us = <500>;
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min-residency-us = <950>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
entry-latency-us = <600>;
|
|
exit-latency-us = <1100>;
|
|
min-residency-us = <2700>;
|
|
wakeup-latency-us = <1500>;
|
|
};
|
|
|
|
CPU_RETENTION_1_0: cpu-retention-1-0 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x0010000>;
|
|
entry-latency-us = <20>;
|
|
exit-latency-us = <40>;
|
|
min-residency-us = <90>;
|
|
};
|
|
|
|
CLUSTER_RETENTION_1: cluster-retention-1 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
entry-latency-us = <50>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <270>;
|
|
wakeup-latency-us = <100>;
|
|
};
|
|
|
|
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
arm,psci-suspend-param = <0x0010000>;
|
|
entry-latency-us = <70>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <300>;
|
|
wakeup-latency-us = <150>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
entry-latency-us = <500>;
|
|
exit-latency-us = <1200>;
|
|
min-residency-us = <3500>;
|
|
wakeup-latency-us = <1300>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
Example 2 (ARM 32-bit, 8-cpu system, two clusters):
|
|
|
|
cpus {
|
|
#size-cells = <0>;
|
|
#address-cells = <1>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x0>;
|
|
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x1>;
|
|
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x2>;
|
|
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x3>;
|
|
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
|
};
|
|
|
|
CPU4: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x100>;
|
|
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
|
};
|
|
|
|
CPU5: cpu@101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x101>;
|
|
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
|
};
|
|
|
|
CPU6: cpu@102 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x102>;
|
|
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
|
};
|
|
|
|
CPU7: cpu@103 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x103>;
|
|
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
|
};
|
|
|
|
idle-states {
|
|
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
entry-latency-us = <200>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <400>;
|
|
wakeup-latency-us = <250>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
entry-latency-us = <500>;
|
|
exit-latency-us = <1500>;
|
|
min-residency-us = <2500>;
|
|
wakeup-latency-us = <1700>;
|
|
};
|
|
|
|
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
entry-latency-us = <300>;
|
|
exit-latency-us = <500>;
|
|
min-residency-us = <900>;
|
|
wakeup-latency-us = <600>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
|
compatible = "arm,idle-state";
|
|
local-timer-stop;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <2000>;
|
|
min-residency-us = <6500>;
|
|
wakeup-latency-us = <2300>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
===========================================
|
|
5 - References
|
|
===========================================
|
|
|
|
[1] ARM Linux Kernel documentation - CPUs bindings
|
|
Documentation/devicetree/bindings/arm/cpus.txt
|
|
|
|
[2] ARM Linux Kernel documentation - PSCI bindings
|
|
Documentation/devicetree/bindings/arm/psci.txt
|
|
|
|
[3] ARM Server Base System Architecture (SBSA)
|
|
http://infocenter.arm.com/help/index.jsp
|
|
|
|
[4] ARM Architecture Reference Manuals
|
|
http://infocenter.arm.com/help/index.jsp
|
|
|
|
[5] ePAPR standard
|
|
https://www.power.org/documentation/epapr-version-1-1/
|