192 lines
3.8 KiB
ArmAsm
192 lines
3.8 KiB
ArmAsm
/*
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* BF561 coreB bootstrap file
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*
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* Copyright 2007-2009 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/asm-offsets.h>
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#include <asm/trace.h>
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/*
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* This code must come first as CoreB is hardcoded (in hardware)
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* to start at the beginning of its L1 instruction memory.
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*/
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.section .l1.text.head
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/* Lay the initial stack into the L1 scratch area of Core B */
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#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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ENTRY(_coreb_trampoline_start)
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/* Enable Cycle Counter and Nesting Of Interrupts */
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#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
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R0 = SYSCFG_SNEN;
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#else
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R0 = SYSCFG_SNEN | SYSCFG_CCEN;
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#endif
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SYSCFG = R0;
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/* Optimization register tricks: keep a base value in the
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* reserved P registers so we use the load/store with an
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* offset syntax. R0 = [P5 + <constant>];
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* P5 - core MMR base
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* R6 - 0
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*/
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r6 = 0;
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p5.l = 0;
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p5.h = hi(COREMMR_BASE);
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/* Zero out registers required by Blackfin ABI */
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/* Disable circular buffers */
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L0 = r6;
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L1 = r6;
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L2 = r6;
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L3 = r6;
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/* Disable hardware loops in case we were started by 'go' */
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LC0 = r6;
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LC1 = r6;
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/*
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* Clear ITEST_COMMAND and DTEST_COMMAND registers,
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* Leaving these as non-zero can confuse the emulator
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*/
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[p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
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[p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
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CSYNC;
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trace_buffer_init(p0,r0);
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/* Turn off the icache */
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r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
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BITCLR (r1, ENICPLB_P);
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[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
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SSYNC;
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/* Turn off the dcache */
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r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
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BITCLR (r1, ENDCPLB_P);
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[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
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SSYNC;
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/* in case of double faults, save a few things */
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p1.l = _initial_pda_coreb;
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p1.h = _initial_pda_coreb;
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r4 = RETX;
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#ifdef CONFIG_DEBUG_DOUBLEFAULT
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/* Only save these if we are storing them,
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* This happens here, since L1 gets clobbered
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* below
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*/
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GET_PDA(p0, r0);
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r0 = [p0 + PDA_DF_RETX];
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r1 = [p0 + PDA_DF_DCPLB];
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r2 = [p0 + PDA_DF_ICPLB];
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r3 = [p0 + PDA_DF_SEQSTAT];
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[p1 + PDA_INIT_DF_RETX] = r0;
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[p1 + PDA_INIT_DF_DCPLB] = r1;
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[p1 + PDA_INIT_DF_ICPLB] = r2;
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[p1 + PDA_INIT_DF_SEQSTAT] = r3;
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#endif
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[p1 + PDA_INIT_RETX] = r4;
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/* Initialize stack pointer */
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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/* This section keeps the processor in supervisor mode
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* during core B startup. Branches to the idle task.
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*/
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/* EVT15 = _real_start */
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p1.l = _coreb_start;
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p1.h = _coreb_start;
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[p5 + (EVT15 - COREMMR_BASE)] = p1;
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csync;
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r0 = EVT_IVG15 (z);
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sti r0;
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raise 15;
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p0.l = .LWAIT_HERE;
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p0.h = .LWAIT_HERE;
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reti = p0;
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#if defined(ANOMALY_05000281)
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nop; nop; nop;
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#endif
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rti;
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.LWAIT_HERE:
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jump .LWAIT_HERE;
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ENDPROC(_coreb_trampoline_start)
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#ifdef CONFIG_HOTPLUG_CPU
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.section ".text"
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ENTRY(_coreb_die)
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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R0 = IWR_DISABLE_ALL;
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P0.H = hi(SYSMMR_BASE);
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P0.L = lo(SYSMMR_BASE);
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[P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
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[P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
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SSYNC;
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p0.h = hi(COREB_L1_CODE_START);
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p0.l = lo(COREB_L1_CODE_START);
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jump (p0);
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ENDPROC(_coreb_die)
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#endif
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__INIT
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ENTRY(_coreb_start)
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[--sp] = reti;
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p0.l = lo(WDOGB_CTL);
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p0.h = hi(WDOGB_CTL);
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r0 = 0xAD6(z);
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w[p0] = r0; /* Clear the watchdog. */
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ssync;
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/*
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* switch to IDLE stack.
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*/
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p0.l = _secondary_stack;
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p0.h = _secondary_stack;
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sp = [p0];
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usp = sp;
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fp = sp;
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#ifdef CONFIG_HOTPLUG_CPU
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p0.l = _hotplug_coreb;
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p0.h = _hotplug_coreb;
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r0 = [p0];
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cc = BITTST(r0, 0);
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if cc jump 3f;
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#endif
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sp += -12;
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call _init_pda
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sp += 12;
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#ifdef CONFIG_HOTPLUG_CPU
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3:
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#endif
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call _secondary_start_kernel;
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.L_exit:
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jump.s .L_exit;
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ENDPROC(_coreb_start)
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