343 lines
8.1 KiB
C
343 lines
8.1 KiB
C
/*
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <asm/delay.h>
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL 0x10
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#define DGT_CLK_CTL_DIV_4 0x3
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#define TIMER_STS_GPT0_CLR_PEND BIT(10)
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#define GPT_HZ 32768
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#define MSM_DGT_SHIFT 5
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static void __iomem *event_base;
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static void __iomem *sts_base;
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* Stop the timer tick */
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if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~TIMER_ENABLE_EN;
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int msm_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~TIMER_ENABLE_EN;
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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writel_relaxed(ctrl, event_base + TIMER_CLEAR);
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writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
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if (sts_base)
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while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
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cpu_relax();
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writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
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return 0;
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}
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static void msm_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 ctrl;
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ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Timer is enabled in set_next_event */
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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}
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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static struct clock_event_device __percpu *msm_evt;
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static void __iomem *source_base;
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static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
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{
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return readl_relaxed(source_base + TIMER_COUNT_VAL);
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}
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static struct clocksource msm_clocksource = {
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.name = "dg_timer",
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.rating = 300,
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.read = msm_read_timer_count,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int msm_timer_irq;
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static int msm_timer_has_ppi;
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static int msm_local_timer_setup(struct clock_event_device *evt)
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{
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int cpu = smp_processor_id();
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int err;
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evt->irq = msm_timer_irq;
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evt->name = "msm_timer";
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evt->features = CLOCK_EVT_FEAT_ONESHOT;
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evt->rating = 200;
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evt->set_mode = msm_timer_set_mode;
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evt->set_next_event = msm_timer_set_next_event;
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evt->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
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if (msm_timer_has_ppi) {
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enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
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} else {
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err = request_irq(evt->irq, msm_timer_interrupt,
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IRQF_TIMER | IRQF_NOBALANCING |
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IRQF_TRIGGER_RISING, "gp_timer", evt);
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if (err)
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pr_err("request_irq failed\n");
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}
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return 0;
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}
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static void msm_local_timer_stop(struct clock_event_device *evt)
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{
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evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
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disable_percpu_irq(evt->irq);
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}
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static int msm_timer_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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/*
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* Grab cpu pointer in each case to avoid spurious
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* preemptible warnings
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*/
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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msm_local_timer_setup(this_cpu_ptr(msm_evt));
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break;
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case CPU_DYING:
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msm_local_timer_stop(this_cpu_ptr(msm_evt));
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block msm_timer_cpu_nb = {
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.notifier_call = msm_timer_cpu_notify,
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};
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static u64 notrace msm_sched_clock_read(void)
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{
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return msm_clocksource.read(&msm_clocksource);
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}
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static unsigned long msm_read_current_timer(void)
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{
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return msm_clocksource.read(&msm_clocksource);
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}
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static struct delay_timer msm_delay_timer = {
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.read_current_timer = msm_read_current_timer,
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};
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static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
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bool percpu)
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{
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struct clocksource *cs = &msm_clocksource;
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int res = 0;
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msm_timer_irq = irq;
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msm_timer_has_ppi = percpu;
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msm_evt = alloc_percpu(struct clock_event_device);
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if (!msm_evt) {
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pr_err("memory allocation failed for clockevents\n");
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goto err;
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}
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if (percpu)
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res = request_percpu_irq(irq, msm_timer_interrupt,
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"gp_timer", msm_evt);
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if (res) {
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pr_err("request_percpu_irq failed\n");
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} else {
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res = register_cpu_notifier(&msm_timer_cpu_nb);
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if (res) {
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free_percpu_irq(irq, msm_evt);
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goto err;
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}
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/* Immediately configure the timer on the boot CPU */
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msm_local_timer_setup(raw_cpu_ptr(msm_evt));
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}
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err:
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writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
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res = clocksource_register_hz(cs, dgt_hz);
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if (res)
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pr_err("clocksource_register failed\n");
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sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
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msm_delay_timer.freq = dgt_hz;
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register_current_timer_delay(&msm_delay_timer);
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}
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#ifdef CONFIG_ARCH_QCOM
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static void __init msm_dt_timer_init(struct device_node *np)
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{
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u32 freq;
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int irq;
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struct resource res;
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u32 percpu_offset;
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void __iomem *base;
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void __iomem *cpu0_base;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("Failed to map event base\n");
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return;
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}
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/* We use GPT0 for the clockevent */
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irq = irq_of_parse_and_map(np, 1);
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if (irq <= 0) {
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pr_err("Can't get irq\n");
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return;
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}
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/* We use CPU0's DGT for the clocksource */
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if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
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percpu_offset = 0;
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if (of_address_to_resource(np, 0, &res)) {
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pr_err("Failed to parse DGT resource\n");
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return;
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}
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cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
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if (!cpu0_base) {
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pr_err("Failed to map source base\n");
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return;
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}
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if (of_property_read_u32(np, "clock-frequency", &freq)) {
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pr_err("Unknown frequency\n");
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return;
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}
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event_base = base + 0x4;
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sts_base = base + 0x88;
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source_base = cpu0_base + 0x24;
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freq /= 4;
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writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
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msm_timer_init(freq, 32, irq, !!percpu_offset);
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}
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CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
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CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
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#else
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static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
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u32 sts)
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{
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void __iomem *base;
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base = ioremap(addr, SZ_256);
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if (!base) {
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pr_err("Failed to map timer base\n");
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return -ENOMEM;
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}
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event_base = base + event;
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source_base = base + source;
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if (sts)
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sts_base = base + sts;
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return 0;
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}
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static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
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{
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/*
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* Shift timer count down by a constant due to unreliable lower bits
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* on some targets.
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*/
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return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
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}
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void __init msm7x01_timer_init(void)
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{
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struct clocksource *cs = &msm_clocksource;
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if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
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return;
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cs->read = msm_read_timer_count_shift;
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cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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/* 600 KHz */
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msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
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false);
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}
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void __init msm7x30_timer_init(void)
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{
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if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
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return;
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msm_timer_init(24576000 / 4, 32, 1, false);
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}
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void __init qsd8x50_timer_init(void)
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{
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if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
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return;
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msm_timer_init(19200000 / 4, 32, 7, false);
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}
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#endif
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