185 lines
7.5 KiB
C
185 lines
7.5 KiB
C
/*
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* Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "vpx_dsp/vpx_dsp_common.h"
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void vpx_idct16x16_256_add_neon_pass1(const int16_t *input,
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int16_t *output,
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int output_stride);
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void vpx_idct16x16_256_add_neon_pass2(const int16_t *src,
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int16_t *output,
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int16_t *pass1Output,
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int16_t skip_adding,
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uint8_t *dest,
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int dest_stride);
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void vpx_idct16x16_10_add_neon_pass1(const int16_t *input,
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int16_t *output,
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int output_stride);
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void vpx_idct16x16_10_add_neon_pass2(const int16_t *src,
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int16_t *output,
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int16_t *pass1Output,
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int16_t skip_adding,
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uint8_t *dest,
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int dest_stride);
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#if HAVE_NEON_ASM
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/* For ARM NEON, d8-d15 are callee-saved registers, and need to be saved. */
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extern void vpx_push_neon(int64_t *store);
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extern void vpx_pop_neon(int64_t *store);
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#endif // HAVE_NEON_ASM
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void vpx_idct16x16_256_add_neon(const int16_t *input,
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uint8_t *dest, int dest_stride) {
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#if HAVE_NEON_ASM
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int64_t store_reg[8];
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#endif
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int16_t pass1_output[16*16] = {0};
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int16_t row_idct_output[16*16] = {0};
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#if HAVE_NEON_ASM
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// save d8-d15 register values.
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vpx_push_neon(store_reg);
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#endif
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/* Parallel idct on the upper 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(input, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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vpx_idct16x16_256_add_neon_pass2(input+1,
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row_idct_output,
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pass1_output,
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0,
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dest,
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dest_stride);
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/* Parallel idct on the lower 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(input+8*16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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vpx_idct16x16_256_add_neon_pass2(input+8*16+1,
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row_idct_output+8,
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pass1_output,
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0,
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dest,
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dest_stride);
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/* Parallel idct on the left 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(row_idct_output, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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vpx_idct16x16_256_add_neon_pass2(row_idct_output+1,
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row_idct_output,
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pass1_output,
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1,
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dest,
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dest_stride);
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/* Parallel idct on the right 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(row_idct_output+8*16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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vpx_idct16x16_256_add_neon_pass2(row_idct_output+8*16+1,
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row_idct_output+8,
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pass1_output,
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1,
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dest+8,
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dest_stride);
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#if HAVE_NEON_ASM
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// restore d8-d15 register values.
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vpx_pop_neon(store_reg);
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#endif
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return;
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}
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void vpx_idct16x16_10_add_neon(const int16_t *input,
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uint8_t *dest, int dest_stride) {
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#if HAVE_NEON_ASM
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int64_t store_reg[8];
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#endif
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int16_t pass1_output[16*16] = {0};
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int16_t row_idct_output[16*16] = {0};
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#if HAVE_NEON_ASM
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// save d8-d15 register values.
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vpx_push_neon(store_reg);
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#endif
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/* Parallel idct on the upper 8 rows */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_10_add_neon_pass1(input, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7
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// which will be saved into row_idct_output.
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vpx_idct16x16_10_add_neon_pass2(input+1,
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row_idct_output,
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pass1_output,
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0,
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dest,
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dest_stride);
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/* Skip Parallel idct on the lower 8 rows as they are all 0s */
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/* Parallel idct on the left 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(row_idct_output, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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vpx_idct16x16_256_add_neon_pass2(row_idct_output+1,
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row_idct_output,
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pass1_output,
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1,
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dest,
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dest_stride);
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/* Parallel idct on the right 8 columns */
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// First pass processes even elements 0, 2, 4, 6, 8, 10, 12, 14 and save the
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// stage 6 result in pass1_output.
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vpx_idct16x16_256_add_neon_pass1(row_idct_output+8*16, pass1_output, 8);
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// Second pass processes odd elements 1, 3, 5, 7, 9, 11, 13, 15 and combines
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// with result in pass1(pass1_output) to calculate final result in stage 7.
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// Then add the result to the destination data.
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vpx_idct16x16_256_add_neon_pass2(row_idct_output+8*16+1,
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row_idct_output+8,
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pass1_output,
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1,
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dest+8,
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dest_stride);
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#if HAVE_NEON_ASM
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// restore d8-d15 register values.
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vpx_pop_neon(store_reg);
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#endif
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return;
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}
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